Stacked FET Deep-Via Layout for Lower Cell Height
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the inefficient use of space and potential short circuits due to the expanded width of deep vias connecting stacked field-effect-transistors (FETs), which are required to connect to both the source/drain regions of top and bottom FETs, leading to wasted space and increased cell height.
Innovation Solution
A semiconductor structure with stacked FETs featuring inverted trapezoidal and trapezoidal shaped deep vias, surrounded by dielectric liners, and connected via frontside and backside contacts, which reduces cell height by optimizing the layout and connectivity of the vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single deep via is used to connect both top and bottom FET source/drain regions, then device density is improved, but cell height increases and short circuit risk increases due to expanded via width
Solution Approach 1:
The single deep via is segmented into two separate deep vias: a first deep via connecting the bottom FET source/drain region and a second deep via connecting the top FET source/drain region. This segmentation allows each via to have a smaller, optimized width that reduces cell height and eliminates short circuit risks while maintaining high device density through the stacked FET configuration
Solution Approach 2:
The patent transitions from a vertical stacking approach (single deep via connecting all layers) to a distributed approach where connectivity is established in separate vertical segments. The first deep via is positioned to connect bottom FET regions while the second deep via connects top FET regions, effectively using spatial distribution to reduce the height requirement of individual via structures
2Quantity of substance
If a single deep via is used to connect both top and bottom FET source/drain regions, then device density is improved, but short circuit risk increases due to expanded via width
Solution Approach 1:
By dividing the single deep via into two separate deep vias with different vertical extents, the patent eliminates the need for one via to span the entire height. The first deep via connects bottom FET regions and the second deep via connects top FET regions, ensuring that no single via structure creates short circuit risks while maintaining high device density
Solution Approach 2:
The patent introduces separate via structures as intermediary connection elements for different FET layers. Rather than using one via to mediate connections across all layers (which causes width expansion and short circuit risk), each deep via acts as a dedicated intermediary for specific FET source/drain regions, improving reliability
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure, which includes a first FET layer having a first and a second FET with a first and a second S/D region respectively; a second FET layer having a third and a fourth FET with a third and a fourth S/D region respectively, the second FET layer being on top of the first FET layer; a first deep via extending from a top level that is at or above a top surface of the third and the fourth S/D region to a bottom level that is at or below a bottom surface of the first and the second S/D region, the first deep via having an inverted trapezoidal shape; and a second deep via extending at least from the top level to the bottom level, the second deep via having a trapezoidal shape. A method of manufacturing the same is also provided.