Stacked FET Contact Routing Through Diffusion-Break Isolation
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Solution Overview
Problem
Current integrated circuit (IC) technologies face challenges in scaling beyond 3 nm due to increasing process complexities and costs, as well as difficulties in forming effective contact structures for stacked field effect transistors (FETs).
Innovation Solution
The development of a stacked field effect transistor (FET) device with a diffusion break dielectric fill region, which allows for the creation of contact wiring passing through the diffusion break region to connect terminals between layers, facilitating improved electrical isolation and interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar FET structures are used for scaling, then manufacturing processes remain relatively simple, but drive current and device performance deteriorate at smaller dimensions
Solution Approach 1:
The patent transitions from planar 2D FET structures to three-dimensional nanosheet FET structures, utilizing vertical stacking to achieve higher drive currents at smaller dimensions. The nanosheet configuration enables improved electrostatic control and performance without proportionally increasing manufacturing complexity.
2Reliability
If contact wiring is formed through conventional methods in stacked FETs, then fabrication processes remain straightforward, but electrical isolation and interconnectivity are insufficient
Solution Approach 1:
The contact wiring structure is segmented into multiple distinct components: diffusion break regions that provide electrical isolation, dielectric fill regions that enable planarization, and separate contact openings that connect to specific terminals. This segmentation allows independent optimization of isolation and interconnectivity while maintaining fabrication feasibility.
Solution Approach 2:
The patent applies different material properties and structural characteristics to specific local regions: diffusion break regions use doped semiconductor material for isolation, while dielectric fill regions use insulating material for planarization. This local differentiation enables simultaneous achievement of electrical isolation and proper interconnectivity without compromising ease of manufacture.
Data Source
AI summary
A stacked field effect transistor (stacked-FET) device includes a first layer comprising at least one first layer transistor structure comprising a plurality of first layer terminals, a diffusion break dielectric fill region adjacent to one of the first layer terminals, a second layer overlying and adjacent to the first layer and comprising at least one second layer transistor structure comprising a plurality of second layer terminals, and a contact wiring between the first layer and the second layer passing through the diffusion break dielectric fill region of the first layer and connecting with one of the second layer terminals.