Self-Aligned Protection Diode Structure for Stacked FET ESD Shielding
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Solution Overview
Problem
The challenge in fabricating protection diodes for stacked FETs, particularly in complementary FET designs where n-type and p-type nanowires/nanosheets are vertically stacked, is the difficulty in forming effective diodes that can mitigate plasma-induced damage (PID) and electrostatic discharge (ESD) while protecting the FETs.
Innovation Solution
The semiconductor structure incorporates a protection diode with heavily doped n-type and p-type epitaxial nanosheets that are self-aligned to a gate, forming a PIN diode structure with an intrinsic layer, which allows for the mitigation of plasma damage and ESD by directing current away from the FETs, thereby protecting them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional chip scaling methods are used, then manufacturing complexity and costs increase, but chip scaling continues to slow
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked 3D FINFET configurations, enabling continued chip scaling by utilizing the vertical dimension. This dimensional change allows higher transistor density without proportionally increasing manufacturing complexity, as the stacking approach can be integrated into existing fabrication processes with modified patterning and deposition steps.
2Reliability
If protection diodes are added to stacked FETs, then reliability against PID and ESD improves, but device complexity increases
Solution Approach 1:
The protection diode structure is merged with the stacked FET architecture by sharing common substrates, gates, and interlayer dielectric structures. The first and second stacked FET structures are formed on the same substrate with integrated protection diodes, reducing overall device complexity compared to separate protection structures. This merging approach allows simultaneous protection of multiple FETs while minimizing additional process steps.
Solution Approach 2:
The protection diode structure serves multiple functions: protecting against plasma-induced damage (PID), protecting against electrostatic discharge (ESD), and maintaining electrical isolation between stacked FET structures. The same diode architecture provides both PID protection during manufacturing and ESD protection during operation, eliminating the need for separate protection mechanisms.
3Reliability
If heavily doped epitaxial layers are used in protection diodes, then protection effectiveness against ESD improves, but manufacturing precision requirements increase
Solution Approach 1:
Heavily doped epitaxial layers are formed during the initial substrate preparation stage before FET structure fabrication. The n-type and p-type epitaxial layers are deposited and doped in advance, creating the protection diode structures prior to subsequent processing steps. This preliminary action ensures precise doping concentrations are achieved while simplifying later manufacturing steps, as the critical doping is completed early in the process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the fabrication of protection diodes that effectively shield stacked FETs from PID and ESD, improving the operational reliability and longevity of the semiconductor devices.
Implementation Method 1
forming a PIN diode structure with an intrinsic layer, which allows for the mitigation of plasma damage and ESD by directing current away from the FETs
Implementation Method 2
mitigation of plasma damage and ESD by directing current away from the FETs
Data Source
AI summary
Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a protection diode. The protection diode includes a substrate, a gate, a first nanosheet layer, and a second nanosheet layer. The first nanosheet layer includes a heavily doped n-type epitaxial disposed over the substrate. Additionally, the first nanosheet layer is in contact with the gate. Further, the second nanosheet layer includes a heavily doped p-type epitaxial disposed over the substrate. Additionally, the second nanosheet layer is in contact with the gate. Further, the first nanosheet layer and the second nanosheet layer surround the gate.