Miniaturized Semiconductor Device With Stacked FET And Diode
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Solution Overview
Problem
The miniaturization of semiconductor devices with switching elements and diodes is hindered by the need for higher component densities and the limitations of existing power module designs, which require further reduction in size and complexity.
Innovation Solution
The semiconductor device design features a field effect transistor (FET) and diode configuration with plate-like shapes, where the FET has its source and gate on one surface and drain on another, and the diode has its anode and cathode on opposite surfaces, with specific wiring patterns and electrodes that allow for stacking and reduced mounting area, utilizing silicon carbide for high-temperature operation and nano silver paste for bonding, thereby reducing heat resistance and increasing power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional power module design with side-by-side switching elements and diodes is used, then the device structure is simple, but the component density is insufficient and miniaturization is limited
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement to a three-dimensional stacked configuration where switching elements and diodes are arranged vertically across multiple layers. This dimensional change enables higher component density by utilizing the vertical space above and below each component, effectively multiplying the usable area without increasing the device footprint.
Solution Approach 2:
The patent implements a nested structure where multiple switching elements and diodes are stacked within each other vertically. Each component layer is positioned above or below adjacent components, creating a compact nested arrangement that maximizes component density while maintaining electrical isolation and functional integrity.
2Volume of moving object
If component size is reduced for miniaturization, then the device size decreases, but the heat generation becomes more concentrated and heat dissipation becomes difficult
Solution Approach 1:
The patent assigns different thermal management functions to different regions of the device. The substrate is designed with enhanced thermal conductivity in specific areas to channel heat away from dense component regions. Heat dissipation paths are optimized locally at each component level, allowing efficient heat removal despite the compact overall size and high power density.
Solution Approach 2:
The patent introduces vertical heat dissipation paths through the stacked structure, utilizing the third dimension for thermal management. Heat can escape through multiple levels and surfaces rather than being confined to a single plane, significantly improving heat dissipation efficiency in the miniaturized device.
3Quantity of substance
If more wiring patterns and electrodes are added for the stacked configuration, then the component density increases, but the wiring complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs wiring patterns and electrodes that serve multiple functions simultaneously. Conductive structures are configured to provide both electrical connectivity between stacked components and structural support for the layered architecture. This multi-functionality reduces the total number of separate wiring elements needed, simplifying manufacturing despite the increased component density.
Data Source
AI summary
To realize further miniaturization of a semiconductor device.The semiconductor device 10 is provided with a switching element (FET 14) provided on a substrate 18, a first electrode (electrode 13) provided on an opposite side of the substrate 18 interposing the switching element, a diode 12 provided on an opposite side of the switching element interposing the first electrode, and a second electrode (electrode 11) provided on an opposite side of the first electrode interposing the diode 12.