Stacked FET Dual-Sided Power and Signal Routing
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Solution Overview
Problem
Existing semiconductor manufacturing processes face complexity and routing congestion due to the connection of signal and power lines in stacked FETs, which are typically limited to the front side, leading to inefficiencies.
Innovation Solution
The implementation of power and signal lines on both the front and back sides of vertically stacked FETs, reducing process complexity and improving routing congestion through dual-sided connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power lines and signal lines are connected only on the front side of stacked FETs, then the manufacturing process is simpler, but routing congestion increases and manufacturing efficiency decreases
Solution Approach 1:
The patent extends the routing dimension from a single-sided (front side only) configuration to a dual-sided (front and back sides) configuration. By providing power lines and signal lines on both the front side and back side of the stacked FETs, the invention utilizes the third dimension (vertical stacking combined with bidirectional routing) to increase routing capacity without increasing lateral congestion, thereby improving manufacturing efficiency while maintaining process simplicity.
2Ease of manufacture
If power lines and signal lines are connected only on the front side of stacked FETs, then the manufacturing process is simpler, but routing congestion increases
Solution Approach 1:
The invention resolves routing congestion by transitioning from a two-dimensional single-sided routing approach to a three-dimensional dual-sided routing approach. Power lines and signal lines are now available on both the front side and back side of the stacked FET structure, effectively distributing the routing load across both surfaces and reducing congestion without complicating the manufacturing process.
3Productivity
If dual-sided power and signal lines are implemented in stacked FETs, then routing congestion is reduced and manufacturing efficiency is improved, but device structure becomes more complex
Solution Approach 1:
The dual-sided power and signal line configuration serves multiple functions simultaneously: it reduces routing congestion, improves manufacturing efficiency, and enables more flexible circuit design. The front side and back side lines work together as a unified routing system, providing redundancy and flexibility without requiring fundamentally different manufacturing processes, thus managing structural complexity while delivering multiple benefits.
Data Source
AI summary
A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.