Stacked FET Gate Structure Using a Tri-Layer Dummy Gate
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Solution Overview
Problem
Current semiconductor technologies face challenges in efficiently integrating stacked field-effect transistors (FETs) with separate gate structures, which hinders the reduction of transistor stack area and increases process complexity.
Innovation Solution
The use of a tri-layer dummy gate structure, which includes an upper and lower semiconductor sacrificial layer separated by an etch-stop layer, allows for the formation of both separated and common gate structures in the same integration process, enabling improved control over gate material variations and reduced area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If stacked FETs with separate gate structures are integrated, then gate material variations can be controlled, but the transistor stack area increases and process complexity increases
Solution Approach 1:
The transistor stack is segmented into multiple FETs with separate gate structures, allowing independent control of gate materials for each FET type (n-type and p-type). This segmentation enables precise control over gate material variations by treating each gate as an independent element that can be optimized separately, rather than using a common gate structure for the entire stack.
Solution Approach 2:
The patent implements a nested configuration where multiple FETs are stacked vertically with their channel layers arranged in alternating patterns (n-type channel, p-type channel, n-type channel, etc.). The separate gate structures are nested between these channel layers, with each gate positioned to control its corresponding channel type. This nesting allows compact vertical integration while maintaining separate gate control for each FET.
2Manufacturing precision
If stacked FETs with separate gate structures are integrated, then gate material variations can be controlled, but process complexity increases
Solution Approach 1:
The patent employs a universal fabrication process that can produce both separate gate structures and common gate structures using the same sequence of steps. The process uses alternating sacrificial layer and channel layer formation, followed by gate material deposition that can be configured to create either separate or common gates. This multi-functionality allows the same process tooling and methodology to serve dual purposes, reducing the need for separate process lines.
Solution Approach 2:
Sacrificial layers are deposited in advance during the nanosheet stack formation process, before the actual gate materials are introduced. These sacrificial layers serve as placeholders that define the future gate positions and structures. By preparing the gate structure framework preliminarily through sacrificial layer deposition, the subsequent gate material formation becomes more straightforward and can be configured for either separate or common gate outcomes without adding significant process complexity.
3Device complexity
If conventional integration methods are used, then process complexity is reduced, but transistor stack area increases
Solution Approach 1:
The patent transitions from planar transistor layouts to a three-dimensional stacked configuration, arranging multiple FETs vertically rather than horizontally. The channel layers are stacked in alternating n-type and p-type sequences, with gate structures positioned between these layers. This vertical dimensionality change enables higher transistor density within a smaller footprint area, as the stack utilizes the vertical space above the substrate more efficiently than conventional planar designs.
Solution Approach 2:
The patent merges multiple FET structures into a single integrated stack, combining n-type and p-type FETs in alternating layers within one vertical column. The source and drain regions are merged across adjacent FETs to form shared contact structures, and the gate structures are merged into a unified stack assembly. This merging reduces the overall area required compared to implementing each FET separately in planar configuration.
Data Source
AI summary
Stacked field-effect transistor (FET) devices are provided. A stacked FET device includes a lower FET having lower channel layers and a lower gate material that is between the lower channel layers. The stacked FET device includes an upper FET that is on the lower FET. The upper FET has upper channel layers and an upper gate material that is between the upper channel layers. Moreover, the stacked FET device includes an insulating layer that is between the lower gate material and the upper gate material and not in a region in which the lower channel layers are overlapped by the upper channel layers. Related methods of forming stacked FET devices are also provided.