Stacked FET eDRAM Vertical Integration
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Solution Overview
Problem
Traditional embedded dynamic random access memory (eDRAM) devices face limitations in packing density and have higher fabrication costs due to occupying unique real estate and lower yields, which trade off for larger bandwidth and less power.
Innovation Solution
A method and circuit for implementing an embedded dynamic random access memory (eDRAM) using a stacked field effect transistor (FET) and capacitor, where the capacitor is fabricated directly on top of the FET, utilizing selective metal stack and dielectric deposition techniques for vertical integration, allowing for increased packing density without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional eDRAM devices occupy unique real estate with separate FET and capacitor areas, then bandwidth and power consumption are improved, but packing density decreases and fabrication cost increases
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture by forming the capacitor directly above the FET channel. The capacitor includes a bottom electrode overlapping the source/drain regions, a dielectric layer above the electrode, and a top electrode, creating vertical integration that doubles the functional density within the same footprint area.
Solution Approach 2:
The capacitor structure is nested within the FET area by positioning the bottom electrode of the capacitor to overlap with the source and drain regions of the FET. This nesting allows the capacitor to share physical space with the transistor components, effectively utilizing the same real estate without interfering with FET operation.
2Area of stationary object
If traditional eDRAM devices use separate area for FET and capacitor, then device performance is maintained, but chip area increases
Solution Approach 1:
The patent implements vertical stacking where the capacitor is formed in the z-dimension above the FET channel in the x-y plane. The bottom electrode of the capacitor overlaps the source/drain regions, the dielectric layer extends above, and the top electrode caps the structure, achieving three-dimensional integration that reduces the two-dimensional footprint while maintaining device performance.
3Area of stationary object
If stacked FET and capacitor structure is implemented, then packing density increases and chip area reduces, but fabrication process complexity increases
Solution Approach 1:
The patent combines the FET source/drain regions with the capacitor bottom electrode formation into a single processing step. The same ion implantation or deposition process that creates the FET source/drain regions also forms the bottom electrode of the capacitor, eliminating separate fabrication steps and reducing overall process complexity despite the three-dimensional structure.
Solution Approach 2:
The source and drain regions of the FET serve dual functions: as electrical contacts for the transistor operation and as the bottom electrode for the capacitor. This multi-functionality reduces the number of separate components and fabrication steps required, simplifying the overall manufacturing process while achieving vertical integration.
Data Source
AI summary
A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.