Stacked FET EEPROM with High-k Dielectric
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Solution Overview
Problem
Existing CMOS EEPROM devices face inefficiencies in hot hole injection due to high energy barriers in silicon dioxide gate dielectrics, limiting design possibilities and memory density.
Innovation Solution
The use of high-k gate dielectrics such as silicon nitride, yttrium oxide, zirconium oxide, or hafnium oxide reduces the energy barrier for hot hole and electron injection in nFET and pFET transistors, allowing for efficient avalanche hot-carrier injection and enabling a stacked, parallel configuration of nFET and pFET with a common floating gate, increasing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon dioxide gate dielectric is used in CMOS EEPROM devices, then device stability is maintained, but hot hole injection efficiency deteriorates due to high energy barriers
Solution Approach 1:
The patent changes the material parameter of the gate dielectric from silicon dioxide to high-k materials (silicon nitride, yttrium oxide, zirconium oxide, or hafnium oxide). This parameter change reduces the energy barrier for hot carrier injection while maintaining the insulating properties needed for device stability, thereby resolving the contradiction between reliability and injection efficiency.
Solution Approach 2:
The patent employs composite material structures where high-k gate dielectric materials are integrated with CMOS transistor structures. These composite materials combine the stability characteristics of conventional dielectrics with the high injection efficiency of high-k materials, allowing simultaneous achievement of reliability and productivity improvements.
2Ease of manufacture
If conventional CMOS EEPROM design is used, then manufacturing process is simple, but memory density is limited
Solution Approach 1:
The patent transitions from planar transistor arrangement to a stacked three-dimensional configuration where transistors are vertically arranged. This dimensional change increases the quantity of memory cells per unit area, thereby improving memory density while maintaining compatibility with existing manufacturing processes through vertical stacking rather than lateral expansion.
3Productivity
If high-k gate dielectrics are used to reduce energy barrier, then hot carrier injection efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the gate dielectric into distinct high-k material layers with specific functions - some layers optimized for hot carrier injection and others for electrical insulation. This segmentation allows the device to achieve high injection efficiency without requiring complete redesign of the entire device structure, thereby limiting the increase in complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances programming efficiency and density by allowing comparable hot hole and electron injection efficiencies, enabling higher-density memory arrays with smaller chip sizes and improved programming speeds.
Implementation Method 1
the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate
Implementation Method 2
allowing for efficient avalanche hot-carrier injection and enabling a stacked, parallel configuration of nFET and pFET with a common floating gate
Data Source
AI summary
Semiconductor device, memory arrays, and methods of writing information to a memory cell include or utilize one or more memory cells. The memory cell(s) include a first transistor located on top of a substrate and connected to a first terminal, a second transistor located on top of the first transistor and connected in parallel to the first transistor and connected to a second terminal, where the first and second transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.