Stacked FET Backside Contact Through Epitaxy for Lower Via Aspect Ratio
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Solution Overview
Problem
Existing semiconductor devices with stacked field effect transistors face challenges in connecting the stacked FETs with a backside power distribution network without requiring contacts that circumvent the bottom and top FETs, leading to increased via aspect ratios and reduced scalability.
Innovation Solution
The semiconductor device incorporates a backside contact that electrically connects the backside power distribution network with the top source/drain epitaxy by cutting through the bottom source/drain epitaxy with dielectric isolation, and a frontside contact that connects the back-end-of-line layer with the bottom source/drain epitaxy without cutting through the top epitaxy, reducing the cell height and via aspect ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are configured to circumvent the bottom and top FETs to connect the stacked FETs with the backside power distribution network, then electrical connectivity is achieved, but the via aspect ratio increases and scalability is reduced
Solution Approach 1:
The patent transitions from horizontal contact routing (circumventing FETs in the plane) to vertical contact routing (cutting through epitaxy layers in the depth dimension). The backside contact cuts through the bottom source/drain epitaxy to reach the top source/drain epitaxy, changing the contact path from a horizontal circumvention route to a vertical penetration route, thereby reducing via aspect ratio and improving scalability.
Solution Approach 2:
The patent segments the contact structure into multiple parts: a backside contact cutting through the bottom epitaxy, a frontside contact forming at the front surface, and dielectric liners isolating these contacts from the FET channels. This segmentation allows each contact to be optimized independently, with the backside contact providing power distribution network connectivity and the frontside contact providing BEOL connectivity, while dielectric liners ensure proper isolation.
2Reliability
If contacts circumvent the stacked FETs to achieve electrical connection, then connectivity is established, but the cell height increases
Solution Approach 1:
The patent reduces cell height by moving contact routing from the horizontal plane (circumvention) to the vertical dimension (penetration). The backside contact cuts through the bottom source/drain epitaxy layer to establish direct vertical connection to the top source/drain epitaxy, eliminating the need for long horizontal circumvention paths that increase cell height.
3Reliability
If dielectric liners are formed to isolate contacts from epitaxy, then electrical isolation is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent introduces dielectric liners as intermediary layers between the metal contacts and the semiconductor epitaxy. These liners serve as electrical isolators, preventing unwanted current flow between contacts and the FET channels. The frontside opening is lined with a frontside dielectric liner, and the backside opening is lined with a backside dielectric liner, creating proper electrical isolation while maintaining a manageable manufacturing process through standard deposition and etching techniques.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source/drain (S/D) epitaxy and a bottom FET with bottom S/D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S/D epitaxy and cuts through the bottom S/D epitaxy with isolation between the backside contact and the bottom S/D epitaxy.