Stacked FET Source/Drain Epitaxy Isolation With C-Shaped Spacers

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Solution Overview

Problem

In the manufacturing of semiconductor integrated circuits, particularly for nanosheet FETs, the exposure of sacrificial material during the spacer etch back process leads to unwanted epitaxial growth between stacked transistors, causing short circuits.

Innovation Solution

A method involving the formation of C-shaped spacers made of the same material as inner spacers, which are used to vertically separate the nanosheets, preventing epitaxial growth by covering the end surfaces of sacrificial sheets, and the use of middle-dielectric-isolation regions to isolate source/drain regions between transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sacrificial material (e.g., SiGe) is used to separate nanosheet transistors during manufacturing, then device density and scaling are improved, but unwanted epitaxial growth occurs between stacked transistors causing shorts

Engineering Contradiction:
Improvedevice densityVSAvoidtransistor isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A C-shaped spacer structure is introduced as an intermediary element between the sacrificial material and the epitaxial growth interface. The spacer comprises a dielectric material layer conformally deposited over the sacrificial material, creating a physical barrier that prevents direct contact and unwanted epitaxial growth between stacked nanosheet transistors while maintaining the sacrificial material's separation function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The C-shaped spacer is formed preliminarily before the epitaxial growth step. The dielectric material is conformally deposited over the sacrificial material and then partially removed to expose only the sacrificial material at the nanosheet interface, ensuring that the protective barrier is in place before any unwanted epitaxial growth can occur.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If spacer etch back process is performed to expose sacrificial material, then nanosheet separation is improved, but epitaxial growth is inadvertently promoted between transistors

Engineering Contradiction:
Improvenanosheet separationVSAvoidunwanted epitaxial growth
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The C-shaped spacer acts as an intermediary protective layer that remains after the spacer etch back process. While the spacer etch back exposes the sacrificial material for proper nanosheet separation, the C-shaped spacer's dielectric material layer remains as a protective barrier, preventing the exposed sacrificial material from causing unwanted epitaxial growth.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The spacer structure has non-uniform thickness and composition - the C-shaped spacer is formed with dielectric material that is conformally deposited and then selectively removed. This creates a structure where the protective dielectric material is present exactly where needed (over the sacrificial material at the transistor interface) while allowing spacer etch back to proceed elsewhere for proper nanosheet separation.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents short circuits by blocking epitaxial growth and ensures proper isolation between source/drain regions of stacked nanosheet transistors, enhancing the reliability and density of semiconductor devices.

Implementation Method 1

unwanted epitaxial growth between the bottom and the top nanosheet transistors

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20240030284A1Source/drain epitaxy process in stacked fet
Publication Date: 2024.01.25 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20240030284A1 patent drawing
  • US20240030284A1 patent drawing
  • US20240030284A1 patent drawing

AI summary

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a first set of nanosheets and a second set of nanosheets on top of the first set of nanosheets, wherein the first set of nanosheets has an uppermost nanosheet and the second set of nanosheets has a lowermost nanosheet, the lowermost nanosheet being separated from the uppermost nanosheet by a first gap; forming a conformal liner covering the first set of nanosheets and the first gap; covering a first portion of the conformal liner at the first gap with a protective stud; selectively removing a second portion of the conformal liner from end surfaces of the first set of nanosheets; and forming source/drain at the end surfaces of the first set of nanosheets. A structure formed thereby is also provided.