Stacked FET Transition Region Layout to Prevent Epitaxy Shorting
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Solution Overview
Problem
Stacked field-effect transistors (FETs) face challenges such as top-to-bottom source/drain epitaxy shorting and work function metal patterning undercut due to insufficient separation between the top and bottom devices, which can lead to reliability issues and require additional space for interconnection, and increasing the sacrificial layer thickness results in microloading and uniformity issues during inner spacer deposition.
Innovation Solution
Incorporating sacrificial semiconductor layers thinner than the channel layers to increase separation between the top and bottom devices, reducing the risk of microloading and the amount of inner spacer material needed, and using an interlayer dielectric between inner spacers to enhance uniformity and prevent gate pinchoff.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sacrificial layer thickness is increased to separate top and bottom devices, then the risk of source/drain epitaxy shorting is reduced, but microloading and uniformity issues occur during inner spacer deposition
Solution Approach 1:
The patent divides the sacrificial layer into multiple thinner segments (first sacrificial layer and second sacrificial layer) rather than using a single thick layer. This segmentation allows the inner spacer material to be deposited uniformly across each thinner layer without experiencing microloading effects, while still achieving the required total separation distance between top and bottom devices when both sacrificial layers are combined.
2Reliability
If the sacrificial layer thickness is increased to prevent shorting, then device separation is improved, but the amount of inner spacer material needed increases
Solution Approach 1:
By segmenting the sacrificial layers into multiple thinner layers, the inner spacer material is distributed across multiple deposition interfaces rather than requiring a single continuous thick layer. This reduces the total volume of inner spacer material needed while maintaining adequate separation between devices to prevent shorting.
3Manufacturing precision
If thinner sacrificial layers are used to reduce microloading, then inner spacer uniformity is improved, but device separation may be insufficient
Solution Approach 1:
The patent combines multiple thin sacrificial layers (first sacrificial layer and second sacrificial layer) to achieve the total separation distance required between top and bottom devices. Each individual layer is thin enough to avoid microloading issues during inner spacer deposition, but the cumulative thickness of multiple layers provides sufficient device separation to prevent shorting.
Data Source
AI summary
Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.