Stacked Complementary FET Structure for Flexible CMOS Circuits
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Solution Overview
Problem
Implementing complementary pairs of P-type and N-type metal oxide semiconductor field effect transistors (MOSFETs) in printed and flexible electronic circuits is challenging due to the difficulties in adapting conventional CMOS technology from silicon wafers to these applications.
Innovation Solution
The development of electronic structures comprising two field effect transistors (FETs), specifically complementary pairs of N-type and P-type FETs, with distinct semiconductive materials and configurations, suitable for integration into printed and flexible circuits, where the conductivity of both channels is controlled by a common gate voltage, and the use of specific manufacturing methods to create stacked FET configurations with reduced parasitic capacitances and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CMOS technology is implemented on silicon wafers, then high reliability and established manufacturing processes are achieved, but adaptation to printed and flexible electronic circuits becomes problematic and non-trivial
Solution Approach 1:
The patent transitions from planar 2D transistor layouts on silicon wafers to vertically stacked 3D configurations where multiple FET channels are arranged in layers above a common gate electrode. This dimensional change enables adaptation to flexible substrates while maintaining high device density and control efficiency
Solution Approach 2:
The invention divides the semiconductor structure into multiple discrete layers (first semiconductive layer, second semiconductive layer, gate dielectric layers) that can be independently fabricated and assembled. This segmentation allows for modular manufacturing processes suitable for printed electronics, where each layer can be deposited or printed separately onto flexible substrates
2Productivity
If vertically stacked FET configuration is used, then device density and compactness are improved, but parasitic capacitances and manufacturing defects may increase
Solution Approach 1:
Gate dielectric layers are introduced as intermediary materials between the gate electrode and the semiconductive channels. These dielectric layers electrically isolate the gate from the channels while allowing field penetration for control, and they serve as parasitic capacitance reduction elements by minimizing unwanted electrical coupling between adjacent stacked structures
Solution Approach 2:
The patent employs different material properties at different locations: highly conductive materials for gate and contact regions, insulating dielectric materials in intermediate regions to block parasitic paths, and semiconductive materials with optimized carrier mobility in channel regions. This local optimization of material properties reduces overall parasitic effects while maintaining high device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-density electronic circuits with reduced defects and parasitic capacitances, suitable for flexible and printed electronics, by avoiding processing on semiconductor/dielectric interfaces and utilizing a common gate for conductivity control in vertically stacked FETs.
Implementation Method 1
a gate terminal arranged with respect to (e.g. over) the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal
Data Source
AI summary
A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.