Stacked FET Gate Structure With Lower Parasitic Capacitance

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Solution Overview

Problem

Stacked nanosheet field effect transistors (FETs) face issues with high parasitic capacitance due to excessive gate material in the top FET cutout region, which reduces switching speed and requires a gate cut between adjacent cells, limiting cell density and performance.

Innovation Solution

A self-aligned gate is formed with minimal work function metal in the top gate cutout area, reducing parasitic capacitance and eliminating the need for a gate cut between adjacent cells, allowing for closer cell placement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate material is extended into the top FET cutout region, then the gate can span the entire structure, but parasitic capacitance increases and switching speed decreases

Engineering Contradiction:

Improvegate continuityVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The gate structure is segmented into multiple components: bottom FET gate extensions, top FET gate extensions, and an upper gate extension. This segmentation allows the gate material to be distributed strategically, providing continuity where needed while avoiding excess material in the top FET cutout region that would generate parasitic capacitance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the gate structure have different material compositions and thicknesses. The gate material is present in the bottom FET region and top FET region, but minimized or eliminated in the top FET cutout region. This local variation in quality reduces parasitic capacitance while maintaining gate functionality where required.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If a stepped profile is used to accommodate bottom FET contact, then the structure can be formed, but both top and bottom FETs are affected and adjacent cells are impacted

Engineering Contradiction:

Improvecontact formationVSAvoidstepped profile

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The solution moves from a two-dimensional stepped profile in the planar direction to a three-dimensional structure with vertical gate extensions. The upper gate extension spans horizontally across the top FET cutout region, providing the necessary gate continuity without requiring a stepped profile that would complicate the manufacturing of both FETs and impact adjacent cells.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If gate material is present in the top gate cutout area, then gate coverage is complete, but parasitic capacitance increases

Engineering Contradiction:

Improvegate coverage areaVSAvoidparasitic capacitance

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

Gate material is extracted or removed from the top FET cutout region where it would generate parasitic capacitance. The upper gate extension provides the necessary gate coverage and electrical connection without requiring work function metal in the top gate cutout area, thus taking out the harmful element while maintaining functional coverage.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12615817B2Stacked FET with low parasitic-capacitance gate

Publication Date: 2026.04.28 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.