Stacked FET Gate Contact Formation Without Channel Etch Damage

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Solution Overview

Problem

Existing methods for forming a stacked complementary field-effect transistor (CFET) with electrically connected top and bottom gate electrodes face complications, particularly in achieving precise gate-to-gate contact without damaging the top channel layer.

Innovation Solution

A method involving the formation of a sacrificial layer replaced by a dielectric dummy layer, followed by conformal deposition of gate dielectric and etching in a top-down direction to create a gate-to-gate contact trench, using the dummy layer as an etch mask to protect the top channel layer and ensure precise alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a gate-to-gate contact trench is etched to connect top and bottom gate electrodes, then electrical connection between gates is achieved, but the top channel layer may be damaged during etching

Engineering Contradiction:

Improveelectrical connection between gatesVSAvoiddamage to top channel layer

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A dummy layer is introduced as an intermediary protective layer between the etching process and the top channel layer. This dummy layer serves as a sacrificial mask that absorbs the harmful etching effects, preventing direct damage to the channel layer while allowing the gate-to-gate contact trench to be formed. The dummy layer is subsequently removed after serving its protective function.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The dummy layer is formed in advance before the gate-to-gate contact trench etching process. This preliminary action prepares the structure with a protective barrier that will prevent damage during the subsequent etching operation, rather than attempting to protect the channel layer during or after damage occurs.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If conformal deposition of gate dielectric is performed, then high quality film with uniform thickness is achieved, but additional process steps are required

Engineering Contradiction:

Improveuniform thickness of gate dielectricVSAvoidnumber of process steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The conformal deposition process automatically ensures uniform thickness by depositing material evenly across all surfaces simultaneously. The process self-regulates to provide consistent coverage on vertical sidewalls and horizontal surfaces alike, eliminating the need for additional thickness-control steps or manual adjustments.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The deposition approach transitions from planar to three-dimensional conformal coverage, depositing material uniformly on all surfaces (top, bottom, and sidewalls) of the trench structure. This dimensional approach ensures consistent dielectric thickness regardless of surface orientation, achieving precision through geometric deposition rather than post-processing adjustment.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces the risk of damage to the top channel layer and enables precise formation of the gate-to-gate contact, facilitating high-quality film deposition and reliable electrical contact between the top and bottom gate electrodes.

Implementation Method 1

the dummy layer may serve as an etch mask, counteracting etching of the one or more channel layers of the top FET device, arranged below the dummy layer

Methodology Applied

Scientific EffectEtch mask:

Implementation Method 2

A conformal deposition of the gate dielectric facilitates deposition of a high quality film, with uniform thickness and reliable coverage of surfaces in any orientation

Methodology Applied

Scientific EffectConformal deposition: Deposition (physical)

Implementation Method 3

etching back the gate dielectric in a top-down direction... etching the bonding layer

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS12527079B2Method for forming a stacked FET device

Publication Date: 2026.01.13 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)

AI summary

Example embodiments relate to methods for forming a stacked FET device. An example method includes forming a bottom FET device that includes a source, a drain, at least one channel layer between the source and drain, and a bottom gate electrode arranged along the at least one channel layer. The method also includes forming a bonding layer over the bottom FET. Additionally, the method includes forming a top FET device on the bonding layer. Forming the top FET device includes forming a device layer structure. The device layer structure includes at least one channel layer of a channel semiconductor material and a top sacrificial layer of a sacrificial semiconductor material. Further, the method includes replacing the top sacrificial layer with a dummy layer of a dielectric dummy material, forming a gate-to-gate contact trench, depositing gate electrode material, and forming a source and a drain of the top FET device.