Stacked FET Gate Layout for Independent and Shared Control
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Solution Overview
Problem
Conventional approaches fail to efficiently and flexibly produce independent and shared gate contacts in multi-gate stacked field-effect transistor (FET) devices, limiting the design's functionality and flexibility.
Innovation Solution
The implementation of self-aligned gate contacts in stacked FET devices using dielectric sidewall spacers and a dielectric gate cap of a different material, allowing for independent and shared gate control through selective etching, enables the formation of efficient and flexible gate contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple independent gate contacts are employed in a stacked FET device, then the device functionality and control flexibility are improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate contact structure is segmented into multiple independent gates (first gate, second gate, third gate) that can be independently controlled. Each gate is separated by dielectric sidewall spacers, allowing independent electrical control while maintaining a compact stacked configuration. This segmentation enables versatile gate control modes (independent control, shared control, or combined control) without requiring a single complex gate structure.
Solution Approach 2:
Dielectric sidewall spacers are introduced as intermediary elements between adjacent gates. These spacers provide electrical isolation between gates while maintaining precise spatial alignment through self-aligned formation. The spacers act as mediators that enable independent gate control by preventing electrical interference between adjacent gates, thereby increasing control flexibility without proportionally increasing device complexity.
2Adaptability or versatility
If conventional approaches are used for forming gate contacts in stacked FET devices, then the manufacturing process is simpler, but the flexibility in producing independent and shared gate contacts is limited
Solution Approach 1:
Dielectric sidewall spacers are formed preliminarily before gate electrode deposition. This preliminary formation of spacers establishes the spatial framework and alignment references for subsequent gate patterning steps. By pre-defining the positions and dimensions of gate structures through self-aligned spacer formation, the process enables flexible gate configurations (independent or shared) to be achieved through selective etching and material deposition, rather than requiring completely different manufacturing approaches for each configuration type.
Solution Approach 2:
The gate contact structure is designed to be dynamically configurable. The same basic stacked FET structure with multiple gates and dielectric spacers can be adapted to different operational modes (independent gate control, shared gate control, or mixed control) through selective electrical connections and biasing schemes. This dynamic adaptability allows a single manufacturing process to produce devices with varying degrees of gate independence, providing flexibility without requiring multiple specialized fabrication processes.
3Area of moving object
If stacked FET design is implemented, then the footprint area is reduced, but the challenge of integrating multiple independent gates increases
Solution Approach 1:
The FET structure transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. Multiple FET channels are arranged vertically in stacked layers with corresponding gates positioned at different heights. This vertical stacking in the third dimension dramatically reduces the horizontal footprint area while accommodating multiple independent gates. The dielectric sidewall spacers enable this vertical integration by providing isolation between gates at different levels, allowing complex multi-gate functionality to be achieved within a compact volume.
Solution Approach 2:
The stacked FET structure employs a nested arrangement where multiple FET channels and their corresponding gates are positioned concentrically or in overlapping vertical projections. The gates and channels are nested in the vertical dimension, with upper gates positioned above lower gates. This nesting approach maximizes the utilization of vertical space, allowing multiple independent gates to be integrated within a small footprint area by stacking them in a nested configuration rather than spreading them out horizontally.
Data Source
AI summary
Stacked FET devices having independent and shared gate contacts are provided. In one aspect of the invention, a stacked FET device includes: a bottom-level FET(s) having a bottom-level FET gate; a top-level FET(s) having a top-level FET gate, wherein an upper portion of the bottom-level FET gate is adjacent to the top-level FET gate; a dielectric sidewall spacer in between the upper portion of the bottom-level FET gate and the top-level FET gate; and a dielectric gate cap disposed over the bottom and top-level FET gates that includes a different dielectric material from the dielectric sidewall spacer. A device having at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.