Stacked FET Gate Dielectrics for Independent Threshold Tuning
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Solution Overview
Problem
Current stacked field-effect transistors (FETs) face challenges in optimizing gate dielectrics for p-channel and n-channel transistors due to different switching mechanisms, leading to suboptimal electrical performance when using a common gate dielectric material like hafnium oxide in horizontal CMOS architectures.
Innovation Solution
The development of bonded stacked FETs with individually tunable gate dielectrics, where the composition and thickness of the gate dielectrics for the top and bottom transistors can be varied, allowing for independent optimization of the threshold voltage of each transistor, achieved through specific layer configurations and bonding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a common gate dielectric material like hafnium oxide is used in both pFET and nFET transistors, then integration is simplified, but electrical performance is suboptimal for individual transistor types
Solution Approach 1:
The gate dielectric structure is segmented into two separate structures: a first gate dielectric for the pFET and a second gate dielectric for the nFET. These segmented dielectric structures are formed in a stacked configuration, allowing each transistor type to have its own optimized gate dielectric while maintaining vertical integration. This segmentation enables independent optimization of electrical performance for each transistor type without compromising manufacturing simplicity.
Solution Approach 2:
Different gate dielectric materials and thicknesses are applied locally to specific transistor regions. The first gate dielectric is specifically tailored for the pFET with properties optimized for hole conduction, while the second gate dielectric is optimized for the nFET with properties suited for electron conduction. This local quality approach ensures that each transistor receives the appropriate gate dielectric characteristics for its specific switching mechanism.
2Reliability
If individually optimized gate dielectrics are used for pFET and nFET, then electrical performance is improved, but device complexity increases
Solution Approach 1:
The patent transitions from a planar horizontal CMOS architecture to a vertical stacked architecture. By stacking the pFET and nFET vertically with their respective gate dielectrics, the design utilizes the vertical dimension to accommodate individually optimized gate dielectrics without increasing the lateral footprint. This dimensional change allows complex individual optimization to be achieved within a compact integrated structure.
Solution Approach 2:
The gate dielectric structures are nested within a stacked transistor configuration where the first gate dielectric and second gate dielectric are positioned at different vertical levels. The source/drain regions are also nested to interconnect the stacked transistors. This nesting approach allows multiple individually optimized components to be integrated in a compact manner, reducing overall device complexity despite the individual customization of each gate dielectric.
3Area of stationary object
If stacked FET architecture is employed, then device footprint is reduced, but gate dielectric optimization becomes more challenging
Solution Approach 1:
The gate dielectric is segmented into vertically separated first and second gate dielectric structures, each accessible at different levels of the stacked configuration. This segmentation enables independent formation and optimization of each gate dielectric layer during fabrication, simplifying the optimization process despite the compact stacked architecture. Each dielectric can be processed and tuned independently while maintaining the reduced footprint benefits of vertical integration.
Data Source
AI summary
Bonded stacked FETs with individually tunable gate dielectrics are provided. In one aspect, a stacked FET device includes: a bottom transistor disposed on a wafer; and a top transistor bonded on top of the bottom transistor via a bonding layer, where the bottom transistor includes a stack of first active layers, a first gate dielectric disposed on the first active layers, and a first gate electrode disposed on the first gate dielectric, where the top transistor includes a stack of second active layers, a second gate dielectric disposed on the second active layers, and a second gate electrode disposed on the second gate dielectric, and where the first gate dielectric has at least one of a different composition and a different thickness from the second gate dielectric. A method of forming the present stacked FET devices is also provided.