Stacked FET Gate Contact Layout for BEOL Connection
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Solution Overview
Problem
Challenges exist in forming contact wirings for stacked FET devices without increasing the cell height, particularly in connecting the bottom gate to the BEOL interconnect without expanding the gate extension to the active area.
Innovation Solution
A method involving forming a bottom device, creating a gate contact placeholder over the bottom S/D epitaxial region, forming a top device, connecting the top contact to the placeholder, and establishing a backside contact to the bottom S/D epitaxial layer with a gate contact placeholder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact wiring methods are used for stacked FET devices, then electrical connections can be established, but the cell height increases and gate extension to the active area expands
Solution Approach 1:
The patent transitions from planar contact wiring to a three-dimensional stacked architecture where contacts are formed at different vertical levels. The bottom gate contact is formed in the first interlayer dielectric layer while the top gate contact is formed in the second interlayer dielectric layer, utilizing the vertical dimension to establish electrical connections without increasing cell height or gate extension.
Solution Approach 2:
The contact wiring structure is segmented into distinct components: a bottom gate contact extending from the bottom active region through the first interlayer dielectric layer, and a top gate contact extending from the top active region through the second interlayer dielectric layer. This segmentation allows independent optimization of each contact path, enabling reliable electrical connections while maintaining compact cell dimensions.
2Length of stationary object
If gate contact placeholder is formed over bottom S/D epitaxial region, then stacked FET structures can be formed without increasing cell height, but manufacturing process complexity increases
Solution Approach 1:
The bottom gate contact placeholder is formed preliminarily over the bottom source/drain epitaxial region before completing the top FET formation. This preliminary action establishes the foundation for subsequent stacking operations, enabling the top gate contact to be formed directly over the placeholder without requiring additional lateral extension, thereby maintaining compact cell height.
Solution Approach 2:
The bottom gate contact placeholder is nested within the overall stacked FET structure, serving as a foundational element that supports the top FET formation. The placeholder is positioned such that the top gate contact can be formed directly over it, creating a nested configuration where smaller structural elements are integrated within larger ones, reducing overall device footprint.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.