Stacked FET Architecture with Isolated Gate Pockets
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Solution Overview
Problem
Current stacked FET architectures face challenges in manufacturing flexibility, particularly in connecting or isolating N-P gates, achieving multiple threshold voltages, and using different workfunction metals, which are essential for advanced electronic applications.
Innovation Solution
The solution involves creating separate 'pockets' for top and bottom nanosheet FETs with the option to electrically connect N-gates with P-gates using metal strapping, allowing for the use of different workfunction metals and multiple threshold voltages by forming gate stacks with gate dielectric layers and metal gate layers within these pockets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate pockets for top and bottom nanosheet FETs are created with metal strapping options, then manufacturing flexibility and ability to use different workfunction metals is improved, but device complexity and structural requirements increase
Solution Approach 1:
The patent divides the gate structure into separate pockets for top and bottom nanosheet FETs, allowing independent gate formation and material selection. Each pocket can contain different workfunction metals (e.g., titanium nitride for NFET, tungsten for PFET) and be processed independently, enabling manufacturing flexibility without requiring complex integrated gate structures.
Solution Approach 2:
The patent transitions from planar gate structures to vertical stacked architecture with pockets extending in the vertical dimension. This allows gates to be formed at different heights and positions, enabling independent access and processing of top and bottom FET gates while maintaining compact footprint.
2Adaptability or versatility
If multiple threshold voltages are achieved through different workfunction metals, then device performance and functionality are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the gate metal deposition process into separate steps for different pockets. Each pocket receives specific workfunction metal layers tailored to the required threshold voltage characteristics, allowing independent optimization of NFET and PFET gates without cross-contamination or complex sequential processing.
Solution Approach 2:
Different workfunction metals and thicknesses are applied locally to specific pockets based on the required transistor type and threshold voltage. For example, titanium nitride is deposited in NFET pockets while tungsten is deposited in PFET pockets, allowing each region to have optimized electrical characteristics independent of others.
3Productivity
If stacked FET architecture is used to increase density, then transistor density and throughput current are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the pocket structures and spacer layers before depositing the nanosheet stacks and gates. This preliminary structuring establishes precise alignment references that guide subsequent deposition steps, reducing the need for high-precision alignment during critical gate formation processes.
Solution Approach 2:
Dielectric spacer layers serve as intermediary structures that define the vertical and horizontal positioning of nanosheets and gates. These spacers act as self-aligned masks and positioning references, ensuring precise spacing between multiple nanosheets and accurate gate alignment without requiring extreme precision in direct patterning steps.
Data Source
AI summary
A stacked FET architecture includes isolated pockets for replacement metal gates for top and bottom nanosheet field-effect transistors. Different work function metals are employed for the metal gates of n-type and p-type FETs. The architecture allows flexibility in providing electrically connected or unconnected metal gates.