Stacked FET Gate Protrusions for Nanosheet Contact Formation
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Solution Overview
Problem
The challenge of forming contacts to stacked transistors is difficult due to the limited space between devices as they scale down, particularly in nanosheet technology, where device interference and reduced surface area for connections pose issues.
Innovation Solution
The formation of asymmetric source/drain profiles with a dielectric liner on sidewalls and the use of gate protrusions to facilitate contact connections, along with the creation of various contact types to enhance connectivity in stacked FET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If devices are scaled down and placed closer together to increase device density, then device density is improved, but the space between devices becomes limited causing interference and making contact formation difficult
Solution Approach 1:
The patent transitions from planar device arrangement to three-dimensional stacked FET architecture. By stacking multiple FET devices vertically (bottom FET device and upper FET device), the invention increases device density in the vertical dimension while maintaining adequate horizontal spacing for contact formation. The gate protrusion extending from the upper gate into the space between devices enables contact access without requiring additional horizontal space.
Solution Approach 2:
The gate protrusion is nested within the space between the bottom and upper FET devices. The protrusion extends downward from the upper gate and partially overlaps with both the bottom gate cut region and upper gate cut region, effectively utilizing the vertical space that would otherwise be empty. This nesting approach enables contact formation without increasing the device footprint.
2Ease of manufacture
If symmetric source/drain profiles are used in stacked FET devices, then manufacturing is simpler, but contact surface area is reduced making connections difficult
Solution Approach 1:
The patent employs asymmetric source/drain profiles where the third and fourth source/drain regions have different dimensions. Specifically, one source/drain has a narrow section while the other has a wide section. This asymmetry increases the total contact surface area available for connections while maintaining manufacturability through selective etching and deposition processes on different sides of the channel.
Solution Approach 2:
The dielectric liner is applied selectively on the sidewalls of the source/drain regions, creating local quality differences. The liner provides structural support and defines the asymmetric profile in specific locations (narrow section and wide section) while leaving other regions unaffected. This localized modification enables increased contact surface area without complicating the overall manufacturing process.
3Reliability
If gate protrusions are used to extend from upper gate to connect with bottom gate, then contact connectivity is improved, but device complexity increases
Solution Approach 1:
The gate protrusion serves multiple functions simultaneously: it provides the electrical connection between the upper and bottom gates, defines the contact region geometry, and acts as a structural support element. By combining these functions into a single feature, the invention improves connectivity without proportionally increasing device complexity. The protrusion is formed using standard semiconductor fabrication processes extending the gate electrode into the inter-device space.
Data Source
AI summary
A microelectronic structure including a first stacked FET device that includes a first bottom FET device and a first upper FET device. The first bottom FET device include a plurality of first bottom channel layers, and the first upper FET device includes a plurality of first upper channel layers. A bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. A gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. The gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.