High-Speed FET Switch Gate Reset for Parasitic Capacitance
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Solution Overview
Problem
High-speed switches used in applications like transceivers face increased switching times due to parasitic capacitance in stacked FETs, which affects their performance in handling high power signals.
Innovation Solution
A method and apparatus that involve coupling the gate of a field effect transistor (FET) to a reference potential during a reset period to minimize charge accumulation, thereby reducing the loading effect on the power supply and speeding up switching time by resetting the FET to ground before activating or deactivating the switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of stacked FETs is increased to handle high power signals, then the power handling capability is improved, but the switching time increases due to increased parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by resetting the gate voltage to a reference potential (ground) before the actual switching operation. This pre-charging or pre-discharging of the gate capacitance during a reset period reduces the charge that needs to be transferred during switching, thereby decreasing switching time while maintaining the stacked FET configuration for high power handling
Solution Approach 2:
The patent applies preliminary anti-action by anticipating the capacitive loading effect and counteracting it in advance through the reset mechanism. By pre-establishing the gate at a known potential state, the system prepares for the upcoming switching event, reducing the adverse effect of parasitic capacitance on switching speed
2Power
If the total width of FETs is increased to maintain low ON resistance with more stacked FETs, then the power handling capability is improved, but the parasitic capacitance increases resulting in longer switching time
Solution Approach 1:
The reset mechanism performs preliminary action by pre-charging or pre-discharging the increased gate capacitance before switching occurs. This allows the larger capacitance (resulting from wider FETs) to be managed more efficiently, reducing the switching time penalty while maintaining the low ON resistance required for high power handling
3Power
If stacked FETs are used to handle high power signals, then the power handling capability is improved, but the capacitive loading at driver outputs increases resulting in increased switching time
Solution Approach 1:
The patent applies preliminary action at the driver output by implementing a reset mechanism that pre-prepares the gate voltage state before switching. This reduces the capacitive loading effect on the driver during the actual switching event, allowing the driver to switch faster while still supporting the high power handling capability provided by the stacked FETs
Solution Approach 2:
The reset mechanism applies preliminary anti-action by anticipating and counteracting the capacitive loading effect before it impacts switching performance. By pre-establishing the gate at a reference potential, the system prepares for the high capacitive load, reducing the adverse effect on switching speed while maintaining high power handling capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces switching time and voltage source settling time by minimizing the load on the power supply, allowing the switch to transition more quickly between states.
Implementation Method 1
The increased parasitic capacitance of the gates when the FETs are stacked results in an increase in switching time
Data Source
AI summary
A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.