Stacked FET Switch Gate Reset for Faster High-Power Switching
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Solution Overview
Problem
High-power switches, particularly those using stacked field effect transistors, face increased switching times due to parasitic capacitance, which affects their performance in handling high-power signals and capacitive loading at the outputs of the drivers.
Innovation Solution
Implementing a reset circuit that couples the gate of the FET to a reference potential during a reset period to minimize charge accumulation, thereby reducing the load on the power supply and speeding up switching time by disconnecting the driver from the gate and reconnecting it after the reset period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If stacked FETs are used to increase power handling capability, then power handling capability is improved, but switching time increases due to increased parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by implementing a reset circuit that pre-charges or pre-discharges the gate of the stacked FETs before the actual switching operation. This preliminary charge state preparation reduces the amount of charge that needs to be transferred during switching, thereby decreasing switching time while maintaining the power handling capability provided by the stacked FET configuration
Solution Approach 2:
The reset circuit acts as an intermediary between the power supply and the gate of the stacked FETs. It provides a dedicated charge/discharge path that is separate from the main switching path, allowing the gate to be prepared in advance without affecting the power supply stability during normal operation
2Power
If the number of stacked FETs is increased to handle high power signals, then power handling capability is improved, but capacitive loading at driver outputs increases
Solution Approach 1:
The patent segments the charge transfer function into two separate operations: a preliminary charge/discharge phase handled by the reset circuit, and the main switching phase handled by the driver. This segmentation reduces the capacitive loading burden on the driver by pre-preparing the gate charge state, allowing the driver to perform only the final switching action
3Power
If gate width is increased to compensate for increased ON resistance in stacked FETs, then overall ON resistance is maintained, but parasitic capacitance increases further
Solution Approach 1:
The reset circuit performs preliminary charge/discharge of the gate before switching, which compensates for the increased parasitic capacitance caused by larger gate width. By pre-establishing the appropriate charge state, the actual switching transition is accelerated despite the larger capacitance that would otherwise slow it down
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces switching time and voltage source settling time by minimizing the loading effect on the power supply, allowing the switch to activate or deactivate more quickly.
Implementation Method 1
The increased parasitic capacitance of the gates when the FETs are stacked results in an increase in switching time
Data Source
AI summary
A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.