Stacked FET Gate Via Interconnects for Continued Device Scaling
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Solution Overview
Problem
There is a continued desire for further scaling and reducing the size of field-effect transistors (FETs) beyond current techniques such as fin-shaped channels and stacked nanosheet channels, particularly for next-generation stacked FET devices.
Innovation Solution
The development of gate interconnecting structures for stacked FETs, including conductive vias and contact structures through dielectric layers to electrically connect gate regions, allowing for efficient electrical connections between stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET scaling techniques (fin-shaped channels, stacked nanosheet channels) are used, then transistor size reduction is achieved, but further scaling beyond current techniques is limited
Solution Approach 1:
The patent transitions from planar and simple stacked FET architectures to a three-dimensional stacked configuration where multiple FETs are vertically integrated with shared gate structures. This dimensional evolution enables further size reduction by utilizing vertical space more efficiently while maintaining electrical performance through sophisticated gate interconnect designs that navigate the third dimension.
Solution Approach 2:
The patent implements nested gate structures where gate regions are positioned at different vertical levels and interconnected through conductive vias. The gate interconnect system nests conductive pathways within dielectric layers, creating a compact hierarchical structure that allows multiple gate regions to be electrically connected in a space-efficient manner, enabling continued scaling.
2Area of stationary object
If transistor density is increased through stacking, then device area footprint is reduced, but electrical connection complexity between stacked gate regions increases
Solution Approach 1:
The patent divides the gate interconnect system into discrete segments: gate regions at different levels, dielectric layers separating these regions, and conductive vias providing electrical pathways. This segmentation allows each component to be optimized independently while maintaining overall system functionality, managing complexity through modular design rather than monolithic structures.
Solution Approach 2:
The patent introduces dielectric layers as intermediary structures between stacked gate regions, with conductive vias acting as mediators to establish electrical connections through these dielectric barriers. This intermediary approach manages electrical connection complexity by providing controlled pathways through insulating materials, enabling vertical integration without direct gate-to-gate contact.
3Length of moving object
If gate interconnect structures are added to enable stacked FET connections, then further FET scaling is enabled, but device structure complexity increases
Solution Approach 1:
The patent designs gate interconnect structures that serve multiple functions: electrical connection between stacked gate regions, spatial separation of gates through dielectric layers, and structural framework supporting the stacked FET architecture. This multi-functionality reduces the need for separate dedicated structures for each function, managing overall device complexity while enabling continued FET scaling.
Data Source
AI summary
A semiconductor device comprises a first transistor structure comprising a first gate region and a second gate region, a first dielectric layer disposed between the first gate region and the second gate region, a second transistor structure stacked on the first transistor structure and comprising a third gate region and a fourth gate region, and a second dielectric layer disposed between the third gate region and the fourth gate region. A conductive via is disposed through at least one of the first dielectric layer and the second dielectric layer, wherein at least one of the first gate region and the second gate region are electrically connected to at least one of the third gate region and the fourth gate region by the conductive via.