Stacked FET Gate Cut Interconnects for Nanosheet Source/Drain Links
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Solution Overview
Problem
As devices in nanosheet technology scale down, they interfere with each other and it becomes difficult to form connections between different devices, particularly in forming interconnected structures in gate cut regions.
Innovation Solution
A microelectronic structure with stacked device regions and interconnects in gate cut regions, where the interconnects connect source/drain components across different devices, enabling connections between adjacent or separated source/drains within the same cell or between cells, using a process involving multiple layers and placeholders to determine connection configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If devices are scaled down to continue CMOS scaling, then device density and integration are improved, but device interference increases and connection formation becomes difficult
Solution Approach 1:
The patent transitions from planar interconnect formation to three-dimensional interconnect structures by forming contacts through the gate cut region that connect to source/drain regions at different vertical levels. This dimensional change enables connections despite reduced lateral spacing between scaled-down devices.
Solution Approach 2:
The gate cut region serves as an intermediary space that facilitates interconnect formation between adjacent stacked devices. By creating a dedicated removal region between device stacks, the patent enables interconnect access without requiring direct lateral proximity, thus solving the connection formation difficulty caused by device scaling.
2Area of stationary object
If devices are placed closer together to increase density, then area utilization is improved, but device interference and connection difficulty increase
Solution Approach 1:
The patent segments the gate structure by creating a gate cut region that removes portions of the gate between adjacent device stacks. This segmentation isolates the interconnect formation area from the active device regions, enabling reliable connections while maintaining close device spacing for high area utilization.
Solution Approach 2:
The gate cut region acts as an intermediary zone that provides a controlled environment for interconnect formation. This intermediary space allows connections to be established between closely spaced devices without direct interference between the devices themselves, thus maintaining connection reliability despite high density placement.
3Adaptability or versatility
If interconnects are formed in gate cut regions to connect stacked devices, then device connectivity is improved, but manufacturing process complexity increases
Solution Approach 1:
The gate cut region serves multiple functions: it provides structural separation between device stacks, creates access pathways for interconnects, and defines the spatial configuration for contact formation. This multi-functionality reduces the need for additional dedicated structures, thereby limiting the increase in manufacturing complexity despite improved connectivity.
Solution Approach 2:
The gate cut region is formed early in the manufacturing process, before source/drain region formation and interconnect deposition. This preliminary action pre-establishes the connectivity pathway, allowing subsequent steps to proceed with standard processes rather than requiring complex post-formation modifications, thus limiting overall process complexity increase.
Data Source
AI summary
A microelectronic structure including a stacked device region, where stacked device region is comprised of a plurality of top devices and a plurality of bottom devices. Each of the plurality of top devices includes at least one top source/drain. Each of the plurality of bottom devices includes at least one bottom source/drain. A gate cut region located adjacent to the stacked region and an interconnect located in the gate cut region. The interconnect is connected to at least two different devices located in the stacked device region.