Stacked FET Amplifier Gate Networks for Source Impedance Control
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Solution Overview
Problem
Existing stacked FET amplifiers face inefficiencies and reliability issues due to the inability to effectively control imaginary parts of source impedances, leading to phase shifts and non-linear distortion, especially at higher frequencies, which limits their maximum operational frequency.
Innovation Solution
The implementation of reactance compensation networks coupled to the gates of cascode transistors in stacked FET amplifiers, allowing control over both real and imaginary parts of source impedances, thereby aligning current phases and enhancing amplifier performance without requiring access to intermediate nodes, suitable for both standard and merged configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate capacitors are used to distribute RF voltage across drain-source nodes of stacked transistors, then real part of source impedance can be controlled, but imaginary part of source impedance cannot be effectively controlled
Solution Approach 1:
The gate impedance network is segmented into separate real and imaginary components. The real part is controlled by capacitor Cg coupled to the gate, while the imaginary part is controlled by a separate network comprising inductor Lg and capacitor CG in series with the gate. This segmentation allows independent control of both real and imaginary parts of the source impedance.
Solution Approach 2:
An intermediary gate impedance network is introduced between the gate and the transistor to provide reactance compensation. This network acts as a mediator that cancels the imaginary part of the source impedance by introducing an equal and opposite reactance, thereby enabling control over the imaginary component without affecting the real part control mechanism.
2Speed
If stacked FET amplifiers operate at higher frequencies, then bandwidth is extended, but phase shifts and non-linear distortion increase due to uncontrolled imaginary impedance
Solution Approach 1:
The gate impedance network provides preliminary anti-action by pre-compensating for the imaginary part of the source impedance before the signal passes through the transistor. The inductor Lg and capacitor CG are configured to generate a reactance that opposes and cancels the capacitive reactance of the transistor's internal capacitances, thereby preventing phase shifts and non-linear distortion before they occur.
Solution Approach 2:
The gate impedance network acts as a feedback mechanism where the reactance introduced by Lg and CG is designed to counterbalance the frequency-dependent imaginary impedance of the transistor. As frequency increases, the network automatically adjusts its compensating effect to maintain signal integrity and prevent phase shifts.
3Measurement precision
If intermediate nodes are accessed to control reactance, then source impedance can be controlled, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate impedance network serves multiple functions simultaneously: it controls the real part of the source impedance through capacitor Cg, controls the imaginary part through the Lg-CG series network, and provides reactance compensation all through the single gate terminal. This multi-functionality eliminates the need to access intermediate nodes while achieving complete source impedance control.
Solution Approach 2:
The gate impedance network is self-contained and connects exclusively to the gate terminal of the transistor. It generates its own compensating reactance internally through the Lg and CG components, eliminating the need for external access to intermediate nodes or additional control mechanisms. The network serves itself by providing both real and imaginary impedance control through its intrinsic configuration.
Data Source
Figure 1A
Figure 1B
Figure 1C~1D
AI summary
Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network (Zg21, Zgn1) coupled to a gate of a cascode FET transistor (M2, Mn) of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network (Zg22, Zgn2) coupled to the series-connected resistive and capacitive network (Zg21, Zgn1) provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across the stacked FET transistors.