Stacked FET Amplifier Gate RC Network for Impedance Phase Control

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Solution Overview

Problem

Existing stacked FET amplifiers face challenges in controlling both real and imaginary parts of impedance, leading to efficiency losses, non-linear distortion, and reliability issues, especially at higher frequencies due to phase shifts caused by reactive elements within the amplifier stack.

Innovation Solution

The implementation of a series-connected resistive-capacitive network coupled to the gate of each cascode transistor in the amplifier circuit, which controls both the real and imaginary parts of the source impedance, thereby aligning current phases and enhancing amplifier performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If gate capacitors are used to control real part of source impedance in stacked FET amplifiers, then RF voltage distribution can be controlled, but imaginary part of source impedance cannot be controlled leading to phase shifts

Engineering Contradiction:
Improvecontrol of real part of source impedanceVSAvoidcontrol of imaginary part of source impedance
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The impedance control function is segmented into two independent components: gate capacitors (Cg) control the real part of source impedance, while newly introduced gate resistors (Rg) control the imaginary part. This segmentation allows independent optimization of each impedance component without interfering with the other, resolving the contradiction where only real part control was previously available.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Gate resistors (Rg) are introduced as intermediary elements connected to the gate terminals of cascode transistors. These resistors act as mediators that specifically target and control the imaginary (reactive) part of the source impedance, complementing the existing gate capacitor functionality that controls the real part, thereby achieving complete impedance control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If conventional stacked FET amplifier configuration is used, then amplifier gain is achieved, but phase shifts occur at higher frequencies due to uncontrolled imaginary impedance parts

Engineering Contradiction:
Improveamplifier gainVSAvoidphase alignment at higher frequencies
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The gate resistors provide a feedback path that compensates for the reactive effects in the amplifier stack. By controlling the imaginary part of the source impedance, the resistors create a feedback mechanism that counteracts phase shifts, ensuring that currents from stacked transistors remain aligned even at millimeter wave frequencies where such phase shifts would normally degrade reliability.

Inventive Principle:
Principle #23Feedback

3Device complexity

If gate capacitors are shunted at operating frequencies, then RF voltage control is simplified, but impedance distribution across stacked transistors becomes uncontrolled

Engineering Contradiction:
Improvegate capacitor configurationVSAvoidimpedance distribution control
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The gate capacitor and gate resistor are merged into a combined gate impedance network that simultaneously provides both voltage control and impedance distribution functions. Rather than using capacitors alone (which only control real impedance) or shunting them (which simplifies but loses control), the merged RC network at the gate terminal achieves both objectives: simplified RF voltage control and precise impedance distribution across all stacked transistors.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20240388256A1Impedance control in merged stacked FET amplifiers
Publication Date: 2024.11.21 PSEMI CORP
  • US20240388256A1 patent drawing
  • US20240388256A1 patent drawing
  • US20240388256A1 patent drawing

AI summary

Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.