Stacked FET Inner Interconnect Structure for Shorter Conduction Paths
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Solution Overview
Problem
The manufacturing of semiconductor devices becomes increasingly complex with miniaturization, leading to issues such as high yield loss, reduced reliability of electrical interconnection, and low testing coverage, necessitating improvements in device robustness and manufacturing efficiency.
Innovation Solution
The introduction of an inner interconnect structure (IIS) within a semiconductor device, which includes a vertical stack of FETs with a common gate and independently controlled source/drain regions, providing a shorter conduction path and increased connection opportunities, enhancing device performance in terms of size, power, and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnect structures are used in miniaturized semiconductor devices, then manufacturing complexity increases, but electrical connection reliability deteriorates
Solution Approach 1:
The patent transitions from planar interconnect structures to three-dimensional vertically stacked FET configurations with integrated inner interconnect structures. This dimensional change allows electrical connections to be established through vertical pathways rather than lateral routing, improving connection reliability while managing manufacturing complexity through structured vertical integration.
Solution Approach 2:
The inner interconnect structure is nested within the vertically stacked FET configuration, with conductive lines positioned between the stacked FETs. This nesting approach integrates the interconnect structure within the device architecture itself, reducing external connection requirements and improving reliability without proportionally increasing manufacturing complexity.
2Productivity
If device size is reduced for miniaturization, then functional density increases, but manufacturing precision requirements worsen
Solution Approach 1:
The patent achieves increased functional density by stacking FETs vertically in multiple layers rather than expanding laterally. This vertical integration allows higher device density within the same footprint while maintaining manufacturable dimensions, as the stacking approach can be implemented through sequential deposition and patterning processes that are more tolerant to precision variations than lateral miniaturization.
Solution Approach 2:
The device is segmented into multiple stacked FET layers with independent source/drain regions for each layer. This segmentation allows each layer to be formed and controlled independently, reducing the cumulative precision requirements compared to forming a single large-scale integrated structure, while achieving high functional density through vertical stacking.
3Speed
If conventional interconnect paths are used, then device structure is simpler, but conduction path length increases
Solution Approach 1:
The patent implements vertical conduction pathways through the stacked FET layers via the inner interconnect structure, replacing traditional lateral conduction paths. This vertical routing significantly shortens the distance between source and drain regions across layers, improving conduction speed while the structured integration keeps the added complexity manageable.
Solution Approach 2:
The inner interconnect structure acts as an intermediary element that provides direct vertical electrical pathways between the stacked FETs. This intermediary structure eliminates the need for lengthy lateral routing through outer interconnect layers, reducing conduction path length while adding a controlled level of structural complexity that is integrated within the device architecture.
Data Source
AI summary
A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first conductivity type arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second conductivity type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line arranged in a third layer between the first layer and the second layer. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes a recess portion, wherein the first conductive line is at an elevation of the recess portion.