Stacked FET Inner Interconnect Layout for Shorter Conduction Paths
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Solution Overview
Problem
The complexity of manufacturing semiconductor devices at a miniaturized scale leads to increased yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device structure and manufacturing methods to enhance robustness, reduce costs, and shorten processing time.
Innovation Solution
The introduction of an inner interconnect structure (IIS) within a semiconductor device, which provides a shorter conduction path and additional connection opportunities between vertically stacked FETs, improving device performance in terms of size, power, and speed by reducing electrical resistance and allowing for more design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional interconnect structures are used in vertically stacked FETs, then device area can be reduced through stacking, but electrical resistance increases and conduction path lengthens
Solution Approach 1:
The patent introduces an inner interconnect structure that extends in the vertical dimension between stacked FET layers, rather than only using horizontal interconnects in planar layers. This third-dimensional approach shortens the overall conduction path by providing direct vertical connection routes between source/drain regions of adjacent FETs, reducing both path length and electrical resistance while improving interconnection reliability
2Area of moving object
If device size is reduced through miniaturization, then functional density increases, but manufacturing complexity and yield loss increase
Solution Approach 1:
The inner interconnect structure is nested within the vertical stack of FETs, utilizing the internal space between layers rather than adding external interconnect elements. This nested configuration provides additional connection paths without increasing the overall device footprint, enabling more connections within the same area while avoiding the manufacturing complexity associated with external routing structures
3Adaptability or versatility
If conventional outer interconnect structures are used, then device structure remains simple, but design flexibility and connection opportunities are limited
Solution Approach 1:
The interconnect system is segmented into multiple independent paths: outer interconnect structures for lateral connections and inner interconnect structures for vertical connections between stacked FETs. This segmentation provides designers with multiple independent routing options and connection opportunities, significantly increasing design flexibility and versatility without requiring a complete redesign of the entire interconnect system
Data Source
AI summary
A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes an upper portion and a lower portion, and the first conductive line crosses the first gate between the upper portion and the lower portion.