Stacked Field-Effect Transistor Layout With Insulated Gate Overlap
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Solution Overview
Problem
Parasitic capacitance between the gate electrode and source/drain region in integrated circuit devices deteriorates performance, particularly due to overlapping portions of the gate electrode with the source/drain region, which existing technologies have not adequately addressed.
Innovation Solution
The integration of insulating layers under and above the source/drain regions to reduce parasitic capacitance by ensuring non-overlapping portions between the gate electrode and source/drain regions, achieved by forming a bottom insulating layer that overlaps a lower portion of the gate electrode and a top insulating layer that overlaps an upper portion of the gate electrode, thereby reducing the thickness of the source/drain regions and allowing for separate source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode overlaps with the source/drain region to simplify manufacturing, then the manufacturing process is easier, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
An insulating layer is introduced as an intermediary between the gate electrode and the source/drain region. This insulating layer prevents direct electrical interaction (reducing parasitic capacitance) while still allowing the structural overlap needed for simplified manufacturing. The insulating layer acts as a mediator that decouples the electrical harmful effect from the manufacturing benefit.
Solution Approach 2:
The gate structure is segmented into multiple parts: a gate electrode and a separate insulating layer. This segmentation allows the gate electrode to overlap with the source/drain region for manufacturing simplicity, while the insulating layer portion prevents parasitic capacitance by providing electrical isolation. The segmentation enables independent optimization of manufacturing ease and electrical performance.
2Object-affected harmful factors
If the source/drain region thickness is reduced to minimize overlap with the gate electrode, then parasitic capacitance is reduced, but the source/drain region may become too thin for reliable electrical connection
Solution Approach 1:
The insulating layer serves as a mediator that allows the source/drain region to maintain adequate thickness for reliable electrical connection while still achieving parasitic capacitance reduction. The insulating layer enables the source/drain region to be positioned closer to the gate structure without direct electrical overlap, maintaining both electrical reliability and reduced parasitic effects.
3Object-affected harmful factors
If separate source/drain contacts are implemented to reduce parasitic capacitance, then device performance improves, but the device complexity and manufacturing steps increase
Solution Approach 1:
The insulating layer is merged with the gate structure to form an integrated gate assembly. This merging allows separate source/drain contacts to be implemented effectively, as the insulating layer already provides the necessary electrical isolation. The combined gate-insulating layer structure simplifies the overall implementation of separate contacts compared to adding completely independent isolation structures.
Data Source
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AI summary
Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate (122) and a transistor stack on the substrate (122), the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate (122) and the second transistor and the first transistor may include first and second source/drain regions (110, 112), a first channel region (102) between the first and second source/drain regions (110, 112), and a first gate structure (106) on the first channel region (102). A lower surface of the first source/drain region (110) may be higher than a lower surface of the first gate structure (106) relative to the substrate (122).