Stacked Nanosheet FET Insulator Widths for Shared and Independent Gates
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Solution Overview
Problem
Current stacked field-effect transistors (FETs) utilize dielectric insulator layers of uniform width, which prevents both shared gate integration and independent gate devices, necessitating a solution to allow for these functionalities.
Innovation Solution
A semiconductor structure is formed with a first dielectric insulator layer of a different width than a second dielectric insulator layer adjacent to it, enabling both shared gate integration and independent gate devices by varying the width of the insulator layers between stacked FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If uniform width dielectric insulator layers are used in stacked FETs, then manufacturing simplicity is maintained, but both shared gate integration and independent gate devices cannot be achieved
Solution Approach 1:
The patent applies local quality by making different portions of the dielectric insulator layer have different widths. Specifically, a first portion of the dielectric insulator layer has a first width and a second portion has a second width that is greater than the first width. This non-uniform width configuration allows different regions to serve different functions: one region supports shared gate integration while another supports independent gate devices, thereby resolving the contradiction between versatility and complexity.
2Adaptability or versatility
If non-uniform width dielectric insulator layers are used, then shared gate integration and independent gate devices are enabled, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the dielectric insulator layer into distinct portions with different widths. The first portion has a first width and the second portion has a second width greater than the first width. This segmentation allows each portion to be optimized for specific device requirements while maintaining a unified layer structure, thereby enabling versatile device integration without proportionally increasing manufacturing complexity.
Data Source
AI summary
A semiconductor structure includes a first stacked device having a first field-effect transistor containing one or more first nanosheet layers, a second field-effect transistor containing one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further includes a second stacked device adjacent the first stacked device. The second stacked device having a third field-effect transistor containing one or more third nanosheet layers, a fourth field-effect transistor containing one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.