Stacked FET Isolation Dielectrics via Wafer Bonding
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Solution Overview
Problem
The formation of stacked field effect transistor (FET) circuits is challenging due to the complexity of achieving defect-free channel materials and tightly controlled nanosheet shapes, which are essential for optimal electrostatic control and performance, as existing methods like Si/SiGe/Si/SiGe/Si/SiGe/Si stacks face issues with high germanium content causing epitaxial defects and loss of SiGex integrity.
Innovation Solution
The method involves forming a stacked FET circuit by bonding two wafers with dielectric layers using low-temperature epitaxial growth and atomic layer deposition, optimizing the germanium content and growth temperature to avoid defects and maintain physical integrity, and using SOI process technology to create near-perfect isolation dielectrics, allowing for precise control of nanosheet thickness and spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high germanium content is used in Si/SiGe/Si/SiGe/Si/SiGe/Si stacks to improve drive current, then channel material performance is improved, but epitaxial defects increase and SiGex integrity is lost
Solution Approach 1:
The patent changes the germanium content parameter across different SiGe layers, using varying Ge concentrations (e.g., 10%, 20%, 30%) to optimize both drive current and defect reduction. This parameter optimization resolves the contradiction by finding the right balance between high Ge content for current drive and controlled Ge content for defect minimization
Solution Approach 2:
The patent employs composite Si/SiGe/Si structures with multiple alternating layers of silicon and silicon-germanium. This composite approach allows different layers to serve different functions: Si layers provide low-defect channels while SiGe layers provide strain engineering for enhanced carrier mobility, thus improving drive current without sacrificing reliability
2Reliability
If thin nanosheets are used to improve electrostatic control, then electrostatic control is improved, but thickness variations increase due to imperfect selective etching
Solution Approach 1:
The patent performs preliminary epitaxial growth to form Si/SiGe/Si stacks with precisely controlled thicknesses before any etching processes. The selective etching is then used only to release and shape the nanosheets, not to define their thickness. This preliminary formation of thickness-critical layers resolves the contradiction by decoupling thickness control from etching variability
Solution Approach 2:
The patent applies different material compositions and thicknesses to different parts of the structure. The Si channel layers have precise thickness control for electrostatics, while the SiGe sacrificial layers have different properties optimized for selective removal. This local differentiation allows thin nanosheets with controlled thickness to achieve good electrostatic control
3Power
If nanosheets span the entire available cell height to maximize width, then drive current is improved, but parasitic capacitance increases due to breaks required for processing
Solution Approach 1:
The patent transitions from planar 2D FETs to vertically stacked 3D nanosheet FETs. By stacking multiple nanosheets vertically, the effective channel width is increased without requiring breaks in each individual sheet. This dimensional change allows continuous nanosheets to span the full cell height while achieving equivalent current drive to broken sheets, thus reducing parasitic capacitance
4Power
If stacked FETs are formed with multiple nanosheets to improve performance, then drive current and gate control are improved, but process complexity increases
Solution Approach 1:
The patent segments the device into modular Si/SiGe/Si stacks that can be formed using standard epitaxial processes. Each stack unit can be independently formed and then released to create nanosheets. This segmentation allows complex multi-nanosheet structures to be built from simpler, repeatable building blocks, reducing overall process complexity
Solution Approach 2:
The patent uses SiGe sacrificial layers as intermediary materials that facilitate the formation of suspended Si nanosheet channels. The SiGe layers are easily removed by selective etching, leaving behind the desired nanosheet structure. This intermediary approach simplifies the process of creating complex 3D nanosheet architectures compared to direct formation methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in defect-free isolation dielectrics and maintains the integrity of SiGex layers, reducing epitaxial defects and variability, thereby enhancing the performance of stacked FETs by improving electrostatic control and reducing parasitic capacitance.
Implementation Method 1
forming a stacked FET circuit by bonding two wafers with dielectric layers using low-temperature epitaxial growth
Implementation Method 2
forming a stacked FET circuit by bonding two wafers with dielectric layers using low-temperature epitaxial growth and atomic layer deposition
Implementation Method 3
bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer
Data Source
AI summary
A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.