Stacked FET L-Shaped Layout for Cell Height Scaling
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Solution Overview
Problem
Current stacked FET devices face challenges with larger bottom active regions leading to area waste, high risk of contact shorts, and parasitic capacitance due to non-uniform nanosheet widths, which complicates contact formation and increases parasitic capacitance.
Innovation Solution
The implementation of L-shaped epitaxial and contact extensions for both bottom and top transistor regions, along with staggered via and metal line connections, allows for efficient and simplified connections by maintaining equivalent channel regions and avoiding complete overlap, thereby reducing parasitic capacitance and facilitating easier contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional stacked FET layout is used, then device functionality is achieved, but cell height scaling is inefficient and parasitic capacitance is high
Solution Approach 1:
The patent transitions from planar 2D layout to 3D stacked configuration with L-shaped epitaxial layers that extend in multiple dimensions. The bottom and top epitaxial layers are positioned at different vertical levels and connected through staggered vias, utilizing three-dimensional space to reduce parasitic capacitance while improving cell height scaling efficiency.
Solution Approach 2:
The stacked FET structure is divided into distinct segments: bottom epitaxial layer, top epitaxial layer, gate structure, and interconnecting vias. The L-shaped layouts are segmented into horizontal and vertical portions that connect through dielectric layers, allowing independent optimization of each segment to minimize parasitic effects.
2Ease of manufacture
If larger bottom active regions are used in stacked FET, then contact formation is simplified, but area waste increases
Solution Approach 1:
The patent employs asymmetric L-shaped layouts where the bottom and top epitaxial layers have different geometries and positions. The bottom epitaxial layer extends horizontally to facilitate contact formation, while the top epitaxial layer is positioned to optimize device performance. This asymmetric design simplifies contact formation without requiring uniformly large active regions, thereby reducing area waste.
3Productivity
If overlapping L-shaped layouts are used, then connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
Dielectric layers serve as intermediaries between the bottom and top epitaxial layers, providing a structured medium for forming staggered vias and connections. These intermediary layers simplify the manufacturing process by providing defined interfaces and spacing, reducing the complexity of aligning and connecting the L-shaped layouts while maintaining high connection efficiency.
Data Source
AI summary
Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate.