Stacked Complementary FET Layout for Higher Logic Density
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Solution Overview
Problem
The challenge of increasing integration density in semiconductor devices without further reducing feature size, which is approaching physical limits, while maintaining optimal performance of N-type and P-type field effect transistors (NFETs and PFETs).
Innovation Solution
Stacking NFETs over PFETs in an integrated circuit, with channel structures of PFETs formed as thin walls with (110) crystalline planes and NFETs as thin sheets with (100) crystalline planes, allowing for optimized carrier mobility and reduced footprint area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then integration density is improved, but manufacturing difficulty increases and performance deteriorates due to approaching physical limits
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple transistor layers are stacked in the vertical dimension, allowing integration density to increase without further reducing the lateral feature size. This dimensional change enables continued scaling while maintaining manufacturability and performance at existing lithography limits.
Solution Approach 2:
The patent implements nested transistor structures where source/drain regions of lower transistor layers are positioned within or adjacent to channel regions of upper transistor layers. This nesting arrangement maximizes space utilization in the vertical stack, enabling higher integration density without increasing lateral footprint or compromising manufacturing feasibility.
2Quantity of substance
If feature size is reduced to increase integration density, then integration density is improved, but device performance deteriorates
Solution Approach 1:
The patent applies different crystallographic orientations to different transistor types within the stacked structure. NFETs utilize (100) crystalline planes while PFETs utilize (110) crystalline planes. This local optimization of crystal orientation for each transistor type maintains optimal carrier mobility and device performance while achieving high integration density through vertical stacking.
Solution Approach 2:
By moving to vertical stacking in the third dimension, the patent decouples integration density from lateral feature size. This allows performance to be maintained at existing optimal feature sizes while density increases through additional vertical layers, effectively breaking the performance-density tradeoff that plagues planar scaling.
3Reliability
If NFETs and PFETs are optimized independently, then device performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the transistor stack into distinct NFET and PFET layers with independent channel structures and source/drain regions. This segmentation allows independent optimization of each transistor type's crystal orientation and doping profiles while maintaining a unified vertical stack architecture. The segmented design enables performance optimization without proportionally increasing overall device complexity.
Solution Approach 2:
The patent merges multiple transistor layers into a compact vertical stack with shared gate structures and closely integrated source/drain regions. This merging approach achieves independent optimization of NFET and PFET performance while containing complexity through the unified stacked architecture, rather than requiring separate lateral arrangements for each transistor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases integration density and maintains high performance of both NFETs and PFETs, enabling smaller footprint areas and improved carrier mobility.
Implementation Method 1
channel structures of PFETs formed as thin walls with (110) crystalline planes and NFETs as thin sheets with (100) crystalline planes, allowing for optimized carrier mobility
Implementation Method 2
channel structures of PFETs formed as thin walls with (110) crystalline planes and NFETs as thin sheets with (100) crystalline planes, allowing for optimized carrier mobility
Data Source
AI summary
A semiconductor device and a logic device formed of the semiconductor device are provided. The semiconductor device includes a first field effect transistor (FET), disposed on a semiconductor substrate, and including vertically separated first channel structures formed as thin sheets each having opposite major planar surfaces facing toward and away from the semiconductor substrate; and a second FET, disposed on the semiconductor substrate and overlapped with the first FET. A conductive type of the second FET is complementary to a conductive type of the first FET. Second channel structures of the second FET are separately arranged along a lateral direction, and formed as thin walls.