Stacked Vertical-Horizontal FET Layout for Low-Resistance MOL Contacts
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Solution Overview
Problem
Conventional stacked complementary field-effect transistor (CFET) devices face challenges in forming contacts to bottom source/drain epitaxy, leading to high resistance and coupling effects between top and bottom source/drain epitaxies, which slow down the device performance.
Innovation Solution
The approach involves forming bottom horizontal transistors, wafer bonding top channel materials, and creating top vertical transistors, ensuring that source/drain epitaxies of horizontal and vertical transistors do not overlap, allowing direct MOL contact placement over both.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If source/drain epitaxies of horizontal and vertical transistors are allowed to overlap to simplify fabrication, then manufacturing precision is improved, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked configuration. The bottom horizontal FET and top vertical FET are stacked in the vertical dimension, allowing their source/drain regions to be separated in the lateral plane while maintaining close proximity through vertical stacking. This dimensional transition enables direct MOL contact placement without overlapping epitaxies, simultaneously achieving fabrication simplicity and low contact resistance.
2Device complexity
If conventional stacked CFET configuration is used with overlapping source/drain epitaxies, then device integration is simplified, but coupling effects between top and bottom source/drain epitaxies increase, slowing down device performance
Solution Approach 1:
The patent segments the source/drain regions of the bottom horizontal FET and top vertical FET into separate, non-overlapping areas. By using different lateral positions for the source/drain epitaxies while maintaining vertical stacking, the patent eliminates the harmful coupling effects between overlapping epitaxies. This segmentation allows independent optimization of each FET's source/drain regions while maintaining the benefits of stacked integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration facilitates better MOL contact placement and reduces contact resistance, improving device performance by avoiding overlapping source/drain epitaxies.
Implementation Method 1
wafer bonding a semiconductor layer to exposed topmost surfaces
Data Source
AI summary
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and adjacent source/drain regions are provided, where a dummy gate having a gate cut straddles over the nanosheet stack. A semiconductor layer is wafer bonded. A fin is patterned in the semiconductor layer. A source/drain region is formed. A spacer is formed on the bottom source/drain region. A dummy gate is formed on sidewalls of a portion of the fin. A source/drain region is formed. A trench is formed that passes through one dummy gate to the other dummy gate. The dummy gates are removed. Each sacrificial semiconductor material nanosheet is removed. Functional gate structures are formed in regions occupied by the dummy gates and each sacrificial semiconductor material nanosheet.