Bonded Stacked FET Gate Structure for Multi-VT Thermal Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling down to nanoscale levels and addressing thermal degradation issues in gate stacking configurations with multiple threshold voltages and shared gates in three-dimensional transistor architectures.
Innovation Solution
A semiconductor device with stacked transistors featuring a dipole and non-dipole elements, connected by a self-aligned gate connection, and a 3D structure that minimizes thermal degradation and allows for multiple threshold voltages and shared/independent gates in a single unitary structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are stacked in a three-dimensional configuration to increase transistors per unit area, then device density and productivity are improved, but thermal degradation of gate materials and manufacturing complexity worsen
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate, second gate, third gate) at different vertical levels. Each gate can be independently controlled and optimized, allowing thermal management for each segment while maintaining high device density through the stacked configuration.
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional stacked transistors by adding the vertical dimension. Multiple transistor layers are stacked above each other, significantly increasing the number of transistors per unit area while using techniques like self-aligned gate connections to manage the complexity of this dimensional transition.
2Adaptability or versatility
If multiple threshold voltages are implemented in stacked transistors to enhance functionality, then adaptability is improved, but device complexity and manufacturing difficulty worsen
Solution Approach 1:
Different gate structures are applied to different transistor layers based on their specific requirements. For example, the bottom transistor layer may use a first gate structure optimized for one threshold voltage, while upper layers use different gate structures for other threshold voltages. This allows each local region to have the quality needed for its function.
Solution Approach 2:
The stacked transistor structure serves multiple functions simultaneously: it provides high device density through vertical stacking, enables multiple threshold voltages through different gate configurations, and achieves self-aligned connections that simplify manufacturing. The same basic stacked architecture supports various gate implementations for different functional requirements.
3Ease of manufacture
If self-aligned gate connections are used in stacked transistors to simplify manufacturing, then ease of manufacture is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The gate structures are designed with preliminary alignment features that establish reference points before final connection formation. The self-aligned gate connections are pre-configured in the design stage, allowing subsequent manufacturing steps to align to these established references, thereby simplifying the manufacturing process while maintaining high precision through iterative alignment to multiple reference points.
Data Source
AI summary
A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.