Multi-Silicide Stacked FET Structure for Lower Resistance Contacts
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Solution Overview
Problem
In stacked transistors, the limited space for silicide formation leads to higher resistance and capacitance, hindering improved current flow between silicides and transistor components.
Innovation Solution
A multi-silicide structure is implemented, using different silicides for NFETs and PFETs, such as titanium (Ti) for NFETs and ruthenium (Ru) for PFETs, to customize silicides for specific transistors, thereby reducing resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single silicide material is used for both NFET and PFET in stacked transistors, then the device complexity is reduced, but the resistance and capacitance increase due to limited space for silicide formation
Solution Approach 1:
The patent applies local quality by using different silicide materials for different transistor types within the stacked structure. Specifically, titanium silicide (TiSi2) is used for NFETs while ruthenium silicide (RuSi2) is used for PFETs. This allows each transistor type to have optimized electrical properties tailored to its specific requirements, thereby reducing resistance and capacitance locally where needed without increasing overall device complexity
Solution Approach 2:
The patent employs composite materials by combining multiple silicide materials (titanium silicide and ruthenium silicide) within the same stacked transistor structure. This composite approach enables the integration of materials with different electrical characteristics to optimize performance, where TiSi2 provides low resistance for NFETs and RuSi2 provides low capacitance for PFETs, achieving superior overall current flow performance
2Area of stationary object
If silicide formation space is limited in stacked transistors, then the area is reduced enabling higher integration, but the resistance and capacitance increase hindering current flow
Solution Approach 1:
The patent addresses the limited space constraint by implementing local quality optimization through material selection. By using titanium silicide for NFETs and ruthenium silicide for PFETs in the limited available space, each transistor achieves optimal electrical properties despite the constrained area, thereby maintaining low resistance and capacitance for improved current flow
Solution Approach 2:
The patent applies parameter changes by selecting silicide materials with different electrical characteristics to compensate for the limited formation space. The use of TiSi2 with its low resistance property and RuSi2 with its low capacitance property changes the electrical parameters locally, enabling improved current flow performance even when the physical area for silicide formation is constrained
3Reliability
If different silicides are used for NFET and PFET, then the current flow is improved by reducing resistance and capacitance, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the silicide formation process into separate stages for different transistor types. The process segments the deposition and annealing steps to selectively form titanium silicide for NFETs and ruthenium silicide for PFETs, allowing each material to be optimized independently while managing manufacturing complexity through structured process segmentation
4Productivity
If stacked transistor structure is used, then the integration density is increased, but the space for silicide formation is limited leading to higher resistance and capacitance
Solution Approach 1:
The patent resolves the contradiction between high integration density and electrical performance by applying local quality principles within the stacked structure. Different silicide materials are assigned to different transistor types at specific locations in the stack, ensuring that each transistor maintains optimal electrical properties (low resistance for NFETs, low capacitance for PFETs) despite the constrained three-dimensional space
Solution Approach 2:
The patent uses composite materials to achieve both high integration density and superior electrical performance in the stacked transistor structure. By integrating multiple silicide materials (TiSi2 and RuSi2) with complementary electrical properties into the compact stacked architecture, the patent achieves low resistance and capacitance values that enable improved current flow while maintaining high integration density
Data Source
AI summary
A semiconductor structure, a system, and a method of forming a multi-silicide structure for stacked FETs within the semiconductor. The semiconductor structure may include an NFET. The semiconductor structure may also include a PFET. The semiconductor structure may also include an NFET silicide proximately connected to the NFET, where the NFET silicide is a first material. The semiconductor structure may also include a PFET silicide proximately connected to the PFET, where the PFET silicide is a second material different than the first material. The system may include the semiconductor structure. The method may include forming an NFET silicide proximately connected to an NFET, where the NFET silicide is a first material. The method may also include forming a PFET silicide proximately connected to a PFET, where the PFET silicide is a second material different than the first material.