Vertically Stacked FETs with Overlapping Gate Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional CMOS structures for field-effect transistors face challenges in efficiently forming vertically-arranged transistors with overlapping gate structures, which affects the integration and performance of integrated circuits.
Innovation Solution
The method involves forming vertically-arranged field-effect transistors with epitaxially grown source/drain regions and a shared functional gate structure that overlaps with sections of fins, allowing for the creation of vertically stacked transistors with complementary conductivity types, facilitating the fabrication of advanced logic gates like NAND and NOR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar or fin-type CMOS structures are used, then the manufacturing process is well-established and simple, but the transistor integration density and circuit performance are limited due to horizontal current flow orientation
Solution Approach 1:
The patent transitions from traditional horizontal (2D planar) or slightly vertical (fin-type) transistor structures to fully vertical stacked transistor structures. Multiple transistors are arranged vertically one above another, with gate structures extending in the vertical direction, fundamentally changing the spatial dimension of transistor arrangement to achieve higher integration density
2Productivity
If vertically-arranged transistors with overlapping gate structures are formed, then the integration density and circuit performance are enhanced, but the manufacturing precision and alignment requirements become more challenging
Solution Approach 1:
The patent employs preliminary patterning and alignment steps where gate structures are formed with predetermined positions and orientations before transistor stacking. sacrificial structures and alignment markers are introduced in advance to guide the precise positioning of vertical transistor channels and gates, ensuring accurate overlap and alignment throughout the fabrication process
3Reliability
If epitaxial growth is used to form source/drain regions, then the conductivity and material purity are improved, but the process time and temperature requirements increase
Solution Approach 1:
The patent utilizes selective epitaxial growth conditions where temperature, pressure, and gas flow parameters are precisely controlled to optimize growth rate and material quality. By adjusting these parameters, the process achieves high conductivity source/drain regions while minimizing unnecessary process time, balancing reliability requirements with production efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient fabrication of vertically stacked transistors with overlapping gate structures, enhancing the integration and performance of integrated circuits by allowing for the creation of complex logic gates with improved conductivity types.
Implementation Method 1
epitaxially grown source/drain regions
Data Source
AI summary
Structures that include vertically-arranged field-effect transistors and methods for forming a structure that includes vertically-arranged field-effect transistors. A first field-effect transistor includes a section of a first fin, a first source/drain region, and a second source/drain region. The section of the first fin is arranged between the first source/drain region and the second source/drain region of the first field-effect transistor. A second field-effect transistor includes a second fin arranged over the section of the first fin, a first source/drain region, and a second source/drain region. A functional gate structure has an overlapping arrangement with the section of the first fin and also has an overlapping arrangement with a section of the second fin that is arranged between the first source/drain region and the second source/drain region of the second field-effect transistor.