Stacked FET Source/Drain Layout for Lower Gate Parasitic Capacitance
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Solution Overview
Problem
Parasitic capacitance between the gate electrode and the source/drain region in integrated circuit devices, particularly in 3D-stacked FETs, deteriorates the AC performance and is influenced by the overlapping area between these components.
Innovation Solution
Incorporating insulating layers under and/or above the source/drain regions to reduce the overlapping area with the gate electrode, thereby reducing the parasitic capacitance by minimizing the thickness of the source/drain regions in specific portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the source/drain region is made thicker to improve current drive, then the transistor performance improves, but the parasitic capacitance between gate electrode and source/drain region increases
Solution Approach 1:
The source/drain region is designed with non-uniform thickness, being thicker at the contact region for good electrical connection and thinner at the region overlapping with the gate electrode to reduce parasitic capacitance. This local variation in thickness allows simultaneous optimization of current drive and capacitance reduction.
Solution Approach 2:
The solution moves from a two-dimensional planar view to a three-dimensional vertical structure by varying the thickness of the source/drain region in the vertical dimension. This enables independent optimization of horizontal current drive and vertical capacitance overlap.
2Reliability
If the overlapping area between gate electrode and source/drain region is reduced to decrease parasitic capacitance, then AC performance improves, but the effective area for current flow may be reduced
Solution Approach 1:
The source/drain region has different thicknesses at different locations: thinner where it overlaps with the gate electrode to reduce capacitance, and thicker at the contact regions to maintain current flow capability. This local differentiation resolves the contradiction between capacitance reduction and current flow maintenance.
3Reliability
If insulating layers are added under and/or above source/drain regions to reduce parasitic capacitance, then AC performance improves, but device complexity increases
Solution Approach 1:
Insulating layers are introduced as intermediary elements between the gate electrode and source/drain region. These layers act as mediators that reduce the direct electrical interaction and parasitic capacitance while maintaining the functional integrity of the transistor.
Data Source
AI summary
Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and a first gate structure on the first channel region. A lower surface of the first source/drain region may be higher than a lower surface of the first gate structure relative to the substrate.