Stacked Nanosheet FET Structure With a Passive Device for Analog Circuits
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Solution Overview
Problem
Conventional stacked FET devices in semiconductor devices have both PFET and NFET transistors active at the same time, which is unsuitable for analog signal processing that requires only one type of transistor to be active, leading to parasitic noise and elements.
Innovation Solution
A microelectronic structure with a stacked nanosheet transistor device that includes an active FET and a passive FET, where the active FET processes signals and the passive FET mitigates parasitic elements by being always passive, with terminal connections that can be floating, grounded, or half-clamped.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both PFET and NFET transistors are made active in stacked FET devices, then the device can handle complex logic operations, but parasitic noise and elements are introduced in analog signal processing applications
Solution Approach 1:
The patent implements dynamic control of transistor states by introducing a control mechanism that can switch between active and passive configurations. The stacked FET structure allows the second transistor to be dynamically set to a passive state (with source and drain connected together) when analog processing is required, while maintaining the ability to activate both transistors for logic operations. This dynamic reconfiguration resolves the contradiction by adapting the device behavior to the specific application requirements.
2Ease of manufacture
If PFET and NFET are tied together in pairs for conventional logic operations, then standard logic fabrication processes can be used, but the unused transistor contributes parasitic elements to the circuit
Solution Approach 1:
The patent applies local quality modification by changing the connection configuration of specific terminals in the stacked FET structure. The second transistor's source and drain are locally connected together in the passive configuration, creating a specific local property that eliminates its parasitic contributions while maintaining the overall paired structure for manufacturing compatibility. This localized modification allows the device to maintain ease of manufacture through standard paired fabrication while eliminating parasitic elements in the local region where the second transistor connects to the circuit.
3Object-affected harmful factors
If only one type of transistor (PFET or NFET) is used in analog applications, then parasitic noise is reduced, but the device structure becomes less flexible for different circuit configurations
Solution Approach 1:
The patent implements multi-functionality by designing the stacked FET structure to serve multiple purposes: it can operate in a passive configuration for analog signal processing (reducing parasitic noise) and in an active configuration for digital logic operations (providing circuit flexibility). The control mechanism enables the device to universally handle both analog and digital applications, making the structure adaptable to different circuit requirements while maintaining the benefits of reduced parasitic noise when needed.
Data Source
AI summary
A microelectronic structure includes a nanosheet transistor device stack having a first transistor device stacked on a second transistor device. The first transistor device includes a source and drain. The second transistor device includes terminal connections. A gate is shared between the first transistor device and the second transistor device. The first transistor device is configured to conduct a current between the drain and the source based on a voltage on the gate. The terminal connections of the second transistor device are vestigial irrespective of a voltage applied to the gate, such that the second transistor device is always passive.