Stacked FET Passive Attenuator with Delayed Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing variable gain passive attenuators face challenges in achieving high linearity, low insertion loss, and high bandwidth while being area-efficient, particularly due to the use of large FETs which lead to increased parasitic capacitance and higher insertion loss.
Innovation Solution
The implementation of a variable gain passive attenuator with multiple layers of stacked FETs and resistors, controlled by delayed turn-on sequences for the gates of the FETs, to maintain high linearity and reduce FET area, thereby achieving high IP3, low insertion loss, and high frequency operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If large FETs are used to achieve high linearity and low distortion, then linearity is improved, but parasitic capacitance increases and insertion loss increases
Solution Approach 1:
The patent divides the single large FET into multiple smaller FETs connected in parallel. This segmentation maintains the required linearity by distributing the signal across multiple devices while reducing the parasitic capacitance and insertion loss associated with any single large FET. The controller selectively activates appropriate numbers of FETs based on the desired attenuation level.
Solution Approach 2:
The patent transitions from using FETs in a single layer to multiple stacked layers. This dimensional change allows achieving the required attenuation and linearity performance without requiring excessively large individual FETs, thereby reducing parasitic effects while maintaining functionality.
2Area of moving object
If multiple layers of stacked FETs are used to reduce FET area, then area efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the attenuation function across multiple parallel paths with different numbers of FETs. Each path can be independently controlled, allowing area optimization while managing complexity through modular design. The controller selectively activates paths based on required attenuation levels.
Solution Approach 2:
The patent implements dynamic control where the controller selectively activates different numbers of FETs and different parallel paths based on the desired attenuation level. This dynamic operation allows the system to adapt its complexity to the actual requirements, using simpler configurations when possible and more complex ones only when needed.
3Manufacturing precision
If FETs are turned on sequentially with delayed turn-on sequences, then linearity is maintained, but control complexity increases
Solution Approach 1:
The patent applies preliminary action by delaying the turn-on of certain FETs relative to others in a controlled sequence. This ensures that FETs are activated in an order that maintains linearity during the transition, preventing signal distortion that would occur with simultaneous switching. The controller manages this sequencing to achieve smooth, linear transitions.
4Adaptability or versatility
If parallel attenuation paths with different numbers of transistors are used, then attenuation flexibility is improved, but insertion loss increases
Solution Approach 1:
The patent uses partial action by selectively activating only the necessary number of FETs and paths required to achieve the desired attenuation level. Rather than always engaging all available paths, the system activates only what is needed, thereby maintaining attenuation flexibility while minimizing insertion loss by keeping unnecessary paths inactive.
Data Source
AI summary
Provided herein are apparatus and methods for a variable gain passive attenuator with multiple layer attenuation devices. In certain configurations, at least two rows of stacked FETs are layered in blocks, namely H (horizontal) blocks in a hierarchical schematic representation of the variable gain passive attenuator. Each stack of FETs receives a control signal, and by delaying a second control signal with respect to a first control signal, performance and linearity can be enhanced while insertion loss is reduced.