3D Stacked FET Power Distribution for Higher Integration Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for manufacturing semiconductor devices with 3DS FETs and PDN fabrication face challenges in increasing integration density while simplifying the fabrication process.
Innovation Solution
A method for manufacturing semiconductor devices that involves forming a first field-effect transistor on a substrate, followed by the formation of a first isolation layer, a metal layer deposited in a through hole of the isolation layer for power distribution, and a second field-effect transistor on top, with a contact plug connecting the metal layer to the second transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sequential integration is used to manufacture 3DS FETs, then processing simplicity is improved, but integration density and performance are limited
Solution Approach 1:
The patent transitions from planar sequential integration to three-dimensional stacked integration by forming multiple FET layers vertically. The method creates first and second FETs stacked on top of each other with through-holes penetrating through the stack, enabling higher integration density while maintaining processing feasibility through systematic formation steps.
Solution Approach 2:
The patent divides the integrated structure into distinct segments including first FET, second FET, through-holes, and isolation layers. Each component is formed through dedicated processing steps, allowing independent optimization while achieving high overall integration density.
2Productivity
If self-aligned simultaneous integration is used to manufacture 3DS FETs, then integration density and performance are improved, but processing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the first FET and its isolation layer before creating the second FET. Through-holes are formed and filled with metal layers in advance, establishing a structured foundation that simplifies subsequent processing steps and reduces overall complexity.
Solution Approach 2:
The patent introduces intermediary elements including isolation layers and metal-filled through-holes that mediate between the first and second FETs. These intermediaries provide structural support, electrical connection, and process control, enabling complex stacked integration while managing processing complexity.
3Ease of manufacture
If traditional front-side power distribution network is used, then fabrication process is simpler, but integration density is reduced and voltage loss increases
Solution Approach 1:
The patent moves the power distribution network from the traditional front-side planar configuration to a vertical three-dimensional arrangement. Metal layers are formed within through-holes penetrating the FET stack, enabling power distribution in the vertical dimension and achieving higher integration density without sacrificing fabrication simplicity.
4Productivity
If substrate thinning is performed to increase integration density, then device compactness is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
Instead of thinning the substrate to achieve compactness, the patent inverts the approach by building upward with vertically stacked FETs and through-holes. This maintains substrate thickness while achieving high integration density through the vertical arrangement, avoiding the manufacturing difficulties associated with substrate thinning.
Data Source
AI summary
A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.