Stacked FET Contact Structure for Low-Resistance Power Rails
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Solution Overview
Problem
Connecting semiconductor devices to power supplies becomes increasingly challenging as they scale to smaller dimensions and incorporate stacked FET devices, with high resistance and short circuit risks in buried power rail connections.
Innovation Solution
A hybrid power rail structure is formed by creating frontside buried power rails in gate cut regions and connecting them to source/drain regions, followed by forming upper device connections to these rails, ensuring reduced electrical resistance and minimizing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power rail connections are used in scaled semiconductor devices, then device fabrication is simpler, but electrical resistance increases and short circuit risks arise
Solution Approach 1:
The power connection is segmented into multiple independent paths: frontside buried power rails in gate cut regions, sidewall connectors, and top surface connectors. This segmentation creates redundant conduction paths that reduce overall electrical resistance and prevent single-point failures, directly addressing the reliability and energy loss contradiction.
Solution Approach 2:
The invention transitions from conventional planar power connections to a three-dimensional hybrid structure utilizing frontside, sidewall, and top surface connection regions. This dimensional expansion creates multiple conduction pathways through different spatial dimensions, reducing electrical resistance while maintaining fabrication feasibility.
2Productivity
If device dimensions are scaled down, then device density increases, but power rail connection reliability deteriorates
Solution Approach 1:
The power distribution network is divided into multiple segmented connectors distributed across frontside, sidewall, and top surface regions. This segmentation allows power delivery to be maintained across scaled-down devices by distributing the connection load across multiple smaller contact points, preserving reliability while enabling higher device density.
Solution Approach 2:
The connector structure employs a nested configuration where frontside buried rails are positioned in gate cut regions, sidewall connectors wrap around vertical interfaces, and top surface connectors cap the structure. This nested arrangement maximizes space utilization in scaled devices, maintaining reliable power connections within reduced dimensional footprints.
3Loss of energy
If hybrid power rail structure is implemented, then electrical resistance is reduced, but device complexity increases
Solution Approach 1:
The invention merges frontside buried power rail formation, sidewall connector creation, and top surface connector integration into a unified hybrid power distribution system. By combining these connection types into a single integrated structure, the patent achieves reduced electrical resistance through multiple conduction paths while managing overall structural complexity through systematic integration.
4Reliability
If frontside buried power rails are formed in gate cut regions, then electrical connection is improved, but manufacturing precision requirements increase
Solution Approach 1:
The frontside buried power rails are formed in gate cut regions during preliminary fabrication steps before final device assembly. By establishing these power connection pathways early in the manufacturing process, the invention reduces the precision requirements for subsequent steps, as the rail positions are predetermined by the gate cut pattern rather than requiring high-precision later alignment.
Data Source
AI summary
A semiconductor device including a first source/drain region (S/D) located on a frontside of a substrate, wherein the first source/drain region has a first width, a second S/D region located on the frontside of the substrate, wherein the second source/drain region is located above the first source drain region, wherein the second source/drain region has second width, wherein the first width is larger than the second width, a first power rail located on a backside of the substrate, a second power rail located on the backside of the substrate, a first connector in contact with the first source/drain region, wherein the first connector is only in contact with a sidewall of the first source/drain region, and a second connector in contact with the second source/drain region, wherein the second connector is in contact with a top surface and a side surface of the second source/drain region.