3D Stacked FET Power Wiring for Wider Channels Without Taller Cells
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Solution Overview
Problem
Current semiconductor devices face challenges in securing sufficient channel width without increasing cell height in three-dimensional (3D) stacked Field Effect Transistors (FETs), which is crucial for high operating speed and operational accuracy.
Innovation Solution
The design incorporates a back-side wiring layer with alternating power and signal lines, a first FET, a second FET stacked on top, and through-electrodes connecting them, allowing the first and second FETs to share a gate and omitting one through-electrode in the unit cell to maintain channel width without increasing cell height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-electrodes are added to connect power lines in 3D stacked FETs, then electrical connectivity is improved, but cell height increases
Solution Approach 1:
The patent merges the power line connection function into the existing through-electrode structure by having the front-side power line share the same through-electrode path as the signal lines. This integration allows power delivery without adding separate through-electrodes, thus maintaining channel width while achieving electrical connectivity.
Solution Approach 2:
The through-electrodes serve multiple functions: they simultaneously provide signal transmission and power delivery pathways. The front-side power line utilizes the same vertical connection infrastructure as signal lines, making the through-electrode structure multi-functional and avoiding additional height increase.
2Speed
If channel width is increased to improve operating speed, then performance is improved, but device area increases
Solution Approach 1:
The patent transitions from planar 2D FET structures to 3D stacked configurations, utilizing the vertical dimension to increase effective channel width. By stacking multiple FET layers and providing independent back-side and front-side power lines, the design achieves greater total channel width without expanding the lateral device footprint.
3Ease of manufacture
If power line connections are simplified, then manufacturing is easier, but electrical connectivity may be compromised
Solution Approach 1:
The patent combines power line and signal line routing into a unified structure where the front-side power line shares the same through-electrode infrastructure. This merging simplifies the manufacturing process by reducing the number of separate connection structures needed while maintaining reliable electrical connectivity through the shared vertical pathways.
Data Source
AI summary
A 3D stacked FET may include a back-side wiring layer including a first back-side power line and a second back-side power line, a first FET on the back-side wiring layer, a second FET over the first FET, a front-side wiring layer over the second FET, a first through-electrode connecting the first FET to the second FET, and a second through-electrode connecting the front-side and back-side power lines. The front-side wiring layer may extend in a first direction and may include a front-side power line connected to the second back-side power line. The first FET and the second FET may share a gate extending in a second direction. Each of the first FET and the second FET may include a source and a drain respectively on both sides of the gate in the first direction, and a channel between the source and the drain and surrounded by the gate.