Stacked FET Power Rail Layout for Logic-Memory Isolation
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Solution Overview
Problem
Existing stacked FET architectures face challenges in optimizing performance, power efficiency, and scalability due to limitations in lateral scaling and complex interconnectivity, particularly in managing backside power distribution and contact resistance for top FETs, as well as differing power rail requirements for logic and memory circuits.
Innovation Solution
Implementing a semiconductor device with separate power rails for logic and memory arrays, where logic arrays utilize both VDD and GND rails on the backside and memory arrays use one power rail on the backside and one on the frontside, along with vertical stacking of transistors to increase transistor count and integrate heterogeneous materials for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate power rails are implemented for logic and memory arrays, then signal interference is reduced and stability is improved, but device complexity increases
Solution Approach 1:
The power distribution network is segmented into separate VDD and GND rails for logic arrays versus memory arrays. This segmentation isolates the noise-sensitive memory circuits from the switching activity of logic circuits, preventing signal interference and improving overall system stability and reliability.
Solution Approach 2:
Different power rail configurations are applied to different regions of the device: logic arrays receive both VDD and GND rails on the backside, while memory arrays receive one rail on the backside and one on the frontside. This localized differentiation optimizes each region's performance characteristics while managing interference.
2Productivity
If vertical stacking of transistors is implemented, then transistor density is increased and chip efficiency is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The device transitions from planar transistor arrangement to vertical stacking, utilizing the third dimension (depth) to increase transistor density. Multiple transistor layers are stacked vertically with intermediate layers containing contacts and vias, enabling higher chip efficiency without lateral scaling.
3Area of stationary object
If backside power distribution is implemented, then area is saved and scalability is improved, but contact resistance management becomes more complex
Solution Approach 1:
Power distribution is moved from the frontside to the backside of the substrate, utilizing the opposite surface to reduce lateral interconnect length and save area. This three-dimensional power distribution approach improves scalability while managing contact resistance through optimized via structures.
Data Source
AI summary
A semiconductor device includes a memory array including a first ground rail on a backside of the memory array, a first voltage drain to drain (VDD) rail on a frontside of the memory array, and a logic array including a second ground rail on a backside of the logic array. There is a second VDD rail on the backside of the logic array.