Stacked FET RF Switch Biasing for Lower OFF-State Dissipative Loss
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Solution Overview
Problem
Radio-frequency (RF) switches using field-effect transistors (FETs) in an OFF state experience significant dissipative losses due to high impedance, leading to mismatch loss and reduced quality factor in resonant circuits, especially when high voltage is applied, which affects the efficiency of RF signal routing.
Innovation Solution
The implementation of gate-gate, drain-source, and body-body resistors in a biasing architecture for FETs in a stack configuration, which includes a series arm and a shunt arm, to optimize the ON and OFF states of transistors, reducing dissipative losses by increasing Roff to ground and minimizing resistance roll-off over frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If FETs are used in OFF state with high impedance for RF switching, then signal routing capability is achieved, but dissipative losses increase significantly
Solution Approach 1:
The patent introduces biasing circuits with resistors (gate-gate, drain-source, body-body) as intermediary elements to control the electrical state of FETs in the stack. These resistors act as mediators to establish appropriate voltage divisions across the FET terminals, ensuring low impedance in ON state and high impedance in OFF state, thereby reducing dissipative losses while maintaining reliable switching performance.
Solution Approach 2:
The patent changes the electrical parameters (voltage, impedance) of the FETs by implementing a biasing architecture that applies specific voltages to gate, drain, and body terminals. By controlling the gate-to-source voltage and body-to-source voltage, the FETs transition between ON and OFF states with optimized impedance characteristics, reducing energy loss during switching operations.
2Reliability
If high voltage is applied to FETs in OFF state, then signal isolation is improved, but mismatch loss and quality factor degradation increase
Solution Approach 1:
The patent applies different biasing conditions to different parts of the FET structure. Specifically, the body-to-source voltage is optimized independently from the gate-to-source voltage to achieve local optimization of the depletion region characteristics. This local quality control ensures that the FET presents high impedance for signal isolation while minimizing the impact on matching and quality factor.
3Strength
If FETs are configured in stack configuration, then voltage handling capability is improved, but dissipative losses increase due to high impedance in OFF state
Solution Approach 1:
The patent segments the voltage handling function across multiple FETs connected in series (stack configuration), where each FET handles a portion of the total voltage. The biasing circuits are designed to distribute voltages appropriately across each FET in the stack, ensuring that each device operates in its optimal region. This segmentation allows high voltage handling while the biasing resistors ensure low impedance in ON state to minimize dissipative losses.
Data Source
AI summary
Biasing architectures and methods for lower loss switches. In some embodiments, a switching device can include a series arm having transistors implemented in a stack configuration between first and second nodes. The switching device can further include a shunt arm having transistors implemented in a stack configuration between the first node and a ground node. The switching device can further include a bias architecture having a series arm bias circuit and a shunt arm bias circuit. The series arm bias circuit can be configured to bias the transistors of the series arm and include a gate-gate resistor that couples each pair of neighboring transistors. The shunt arm bias circuit can be configured to bias the transistors of the shunt arm and include a gate-gate resistor that couples each pair of neighboring transistors.