Stacked FET Shielded Output Reduces Reverse Coupling
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Solution Overview
Problem
Stacked field-effect transistors experience unacceptably high reverse coupling and return loss, and have lower maximum stable gain due to the use of a single active region, limiting their performance in semiconductor device and integrated circuit fabrication.
Innovation Solution
A structure and method involving a field-effect transistor with a first and second active gate and a drain region, where a back-end-of-line stack with multiple metal levels is formed, including interconnects that provide electrical isolation and reduce reverse coupling by creating a metal shield between the active gates and the drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If stacked field-effect transistors are formed using a single active region, then the device structure is simplified, but reverse coupling and return loss become unacceptably high
Solution Approach 1:
The patent divides the single active region into multiple stacked active regions (first active region, second active region, third active region), each with its own active gate and channel. This segmentation allows independent control and electrical isolation between stages, reducing reverse coupling while maintaining manageable device complexity through systematic structuring.
Solution Approach 2:
The patent introduces intermediate structures including isolation regions between stacked active regions and specific interconnect arrangements (third interconnect positioned between first and second interconnects) that act as mediators to electrically isolate the drain region from upper gates. These intermediaries block reverse coupling paths without requiring complete redesign of the device architecture.
2Object-affected harmful factors
If stacked field-effect transistors are formed with multiple metal levels, then electrical isolation and shielding are improved, but device complexity increases
Solution Approach 1:
The patent designs the back-end-of-line stack with multiple metal levels that serve multiple functions: the first interconnect connects to the first active gate, the second interconnect connects to the second active gate, and the third interconnect connects to the drain region while providing shielding. This multi-functionality reduces the need for additional dedicated shielding structures, balancing isolation performance with device complexity.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple metal levels (first metal level, second metal level) above the transistor structure. The third interconnect is positioned in the vertical direction between the fourth interconnect and the drain region, creating a three-dimensional shielding arrangement that effectively blocks reverse coupling paths without increasing lateral footprint or planar complexity.
3Ease of manufacture
If a single active region is used, then manufacturing is simpler, but maximum stable gain is lower than desirable
Solution Approach 1:
The patent segments the transistor into multiple stacked active regions (first, second, and third active regions) with corresponding active gates, allowing each region to contribute to the overall gain. This segmentation enables the device to achieve higher maximum stable gain through cascaded amplification while maintaining compatibility with standard semiconductor fabrication processes used for multi-layer structures.
Solution Approach 2:
The patent incorporates preliminary isolation structures and interconnect arrangements during the fabrication process, such as positioning the third interconnect between the first and second interconnects in the horizontal direction and between the fourth interconnect and drain region in the vertical direction. These preliminary actions establish electrical isolation paths early in manufacturing, enabling higher gain performance without requiring additional complex fabrication steps.
Data Source
AI summary
Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.