Stacked FET Power Rail Structure for Tight-Pitch Short Isolation
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Solution Overview
Problem
Current stacked field effect transistors (FETs) face challenges in providing reliable power connections due to the high risk of shorts between adjacent structures, especially with reduced device pitches and sizes, making it difficult to meet performance requirements.
Innovation Solution
The implementation of vertically stacked power rails, separated by dielectric spacers, which connect to source/drain regions on different levels of the FETs, providing positive and negative supply voltages while minimizing the risk of shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep contacts or connections are formed from frontside or backside to provide power connections, then power delivery is achieved, but the risk of shorts to gates or other conductive structures increases extremely high
Solution Approach 1:
The patent transitions from traditional vertical deep contacts to a planar power rail architecture where power connections are distributed across the device plane rather than concentrated in deep vertical contacts. Power rails are formed at multiple levels (first level, second level, third level) extending in the planar direction, reducing the need for deep penetrating contacts and thereby reducing short circuit risk to gates and other conductive structures.
Solution Approach 2:
The patent introduces dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) as intermediary materials between power rails and other conductive structures such as gates. These dielectric layers act as insulation barriers that prevent direct electrical contact and potential shorts, while still allowing power delivery through the layered architecture.
2Productivity
If device pitches and device sizes are reduced to increase areal density, then chip capacity increases, but the risk of shorts between adjacent structures increases
Solution Approach 1:
The patent utilizes a three-level power rail architecture that distributes power connections across multiple planar levels rather than relying on compact vertical contacts. This multi-level planar distribution allows for reduced device pitches while maintaining adequate isolation between power connections and other conductive structures, thereby preventing shorts even as device sizes are reduced.
Solution Approach 2:
The patent employs multiple dielectric layers (first, second, and third dielectric layers) as intermediary insulation barriers between power rails and adjacent conductive structures. These dielectric intermediaries provide reliable electrical isolation that prevents shorts between closely spaced structures, enabling higher areal density without sacrificing reliability.
3Area of stationary object
If power rails are vertically stacked to reduce device pitch, then space efficiency improves, but electrical isolation between power rails becomes more difficult
Solution Approach 1:
The patent introduces dielectric layers (first dielectric layer between first and second power rails, second dielectric layer between second and third power rails) as intermediary insulation barriers in the vertical stack. These dielectric intermediaries provide reliable electrical isolation between vertically stacked power rails, preventing shorts while maintaining compact vertical arrangement for reduced device pitch.
Data Source
AI summary
A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and bottom side. A bottom power rail is disposed on the bottom side between source/drain regions of the field effect transistors, and a top power rail is disposed on the top side between source/drain regions of the field effect transistors.