Stacked Nanosheet FET Source/Drain Geometry for Short Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling the epitaxial growth of source/drain regions in stacked nanosheet FETs, particularly in achieving precise height and width control to prevent shorts between adjacent transistors, as existing time-based mechanisms are insufficient for advanced device scaling.
Innovation Solution
A semiconductor structure and method involving the formation of a nanosheet transistor with epitaxially-grown source/drain regions, where a dielectric cap layer is used to create a flat top surface and vertically aligned edges, allowing for precise control and separation between adjacent transistors, and the use of reactive-ion-etching to define the S/D region shape.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If epitaxial growth of source/drain regions is allowed to grow freely, then device density increases, but short circuits occur between adjacent transistors
Solution Approach 1:
A dielectric cap layer is formed over the source/drain regions before epitaxial growth occurs. This preliminary action establishes predetermined boundaries that constrain the subsequent epitaxial growth, ensuring that the source/drain regions expand to the correct dimensions without causing short circuits between adjacent transistors.
Solution Approach 2:
The dielectric cap layer acts as an intermediary structure between the source/drain regions and the surrounding environment. It provides a physical barrier and template that mediates the epitaxial growth process, controlling both the height and lateral expansion of the source/drain regions while maintaining proper spacing between adjacent devices.
2Ease of manufacture
If time-based control mechanism is used for epitaxial growth, then manufacturing simplicity is maintained, but manufacturing precision is insufficient
Solution Approach 1:
The patent replaces the time-based control mechanism with a structure-based control mechanism. Instead of relying on temporal parameters during epitaxial growth, the dielectric cap layer provides a physical template that defines the final dimensions of the source/drain regions. This substitution maintains manufacturing simplicity while dramatically improving dimension control precision.
Solution Approach 2:
The control parameter for epitaxial growth is changed from time-based parameters to structure-based parameters. The dielectric cap layer's thickness, material composition, and geometric configuration become the controlling factors, enabling precise determination of source/drain region dimensions through structural design rather than temporal control.
3Area of stationary object
If source/drain regions grow too wide horizontally, then device area utilization improves, but shorts occur to adjacent nanosheet transistors
Solution Approach 1:
The dielectric cap layer is formed in advance with predetermined lateral dimensions that define the maximum allowable width of the source/drain regions. This preliminary structural definition ensures that during epitaxial growth, the source/drain regions expand horizontally only to the extent permitted by the cap layer's boundaries, maintaining proper isolation from adjacent transistors.
Solution Approach 2:
The dielectric cap layer serves as an intermediary structure that physically separates and isolates adjacent source/drain regions. By positioning the cap layer between neighboring devices, it prevents lateral expansion of source/drain regions into adjacent transistor areas, ensuring reliable electrical isolation while maximizing area utilization within the permitted boundaries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the source/drain region geometry, preventing shorts and ensuring accurate device scaling, even at the 7-nm node and beyond, by forming a flat top surface and vertically aligned edges with the dielectric cap layer, facilitating efficient epitaxial growth and reducing the risk of inter-transistor interference.
Implementation Method 1
a dielectric cap layer is used to create a flat top surface and vertically aligned edges
Implementation Method 2
forming a dielectric cap layer above the first sacrificial layer
Implementation Method 3
epitaxially growing a first S/D region at the at least first end of the first set of nanosheets
Implementation Method 4
the use of reactive-ion-etching to define the S/D region shape
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first nanosheet transistor having a first source/drain (S/D) region; and a second nanosheet transistor on top of the first nanosheet transistor, the second nanosheet transistor having a second S/D region, the second S/D region being separated from the first S/D region by a dielectric cap layer, wherein the first S/D region of the first nanosheet transistor has a substantially flat top surface adjacent to the dielectric cap layer and has at least one vertical edge that is substantially aligned with an edge of the dielectric cap layer. A method of manufacturing the semiconductor structure is also provided.