Stacked Nanosheet FET Source/Drain Layout for Device Separation
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Solution Overview
Problem
Nanosheet technology in CMOS scaling faces issues as devices become smaller and closer together, leading to interference between transistors.
Innovation Solution
A stacked nanosheet FET structure is developed with upper and lower nanosheet transistors, where the upper source/drain is formed during frontside processing and the lower source/drain during backside processing, with differing tip directions and widths to create separation and facilitate contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanosheet devices are scaled down and placed closer together to increase density, then device integration density is improved, but device interference increases
Solution Approach 1:
The source/drain structure is segmented into multiple distinct regions: upper source/drain regions with upper tips, lower source/drain regions with lower tips, and intermediate regions. This segmentation creates physical separation between stacked nanosheet devices, reducing interference while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from planar device layout to three-dimensional stacked architecture. By forming upper and lower source/drain regions at different vertical levels with tips extending in opposite directions, the design utilizes the vertical dimension to separate devices that would otherwise interfere in a two-dimensional plane, enabling higher density without increased interference.
2Stability of the object's composition
If upper and lower source/drain regions are formed with different tip directions and widths, then device separation is improved, but manufacturing complexity increases
Solution Approach 1:
The upper source/drain regions are formed during frontside processing before the lower source/drain regions are formed during backside processing. This preliminary formation of upper regions with specific tip directions and widths establishes a foundation that guides subsequent processing steps, enabling precise device separation while managing manufacturing complexity through sequential rather than simultaneous formation.
Data Source
AI summary
A microelectronic structure that includes a stacked nanosheet FET transistor that includes an upper nanosheet transistor and a lower nanosheet transistor. The upper nanosheet transistor includes an upper source/drain and the upper source/drain includes an upper tip that is pointed in a first direction. The lower nanosheet transistor includes a lower source/drain and the lower source/drain includes a lower tip pointed in a second direction. The first direction is different than the second direction.