Stacked FET Inner Spacer Epitaxy for Short Isolation
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Solution Overview
Problem
Current stacked FET technologies face issues such as direct shorts, over-burden in the top device region, and difficulty in self-aligned integration, which hinder the effective integration density and reliability of semiconductor devices.
Innovation Solution
The implementation of a semiconductor device with a bottom and top device structure featuring silicon sheets, separation layers, and source-drain epitaxy, along with an inner spacer epitaxy and self-aligned source-drain epitaxy spacer, which prevents direct shorts and controls over-burden, enabling simple self-aligned integration through a pinch-off mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked FET structure is implemented to increase integration density, then integration density is improved, but direct shorts occur between devices
Solution Approach 1:
An inner spacer epitaxy layer is introduced as an intermediary between the bottom source-drain epitaxy and the top silicon sheets. This inner spacer acts as a physical barrier that prevents direct shorts while enabling the stacked configuration to achieve higher integration density.
2Productivity
If stacked FET structure is implemented, then integration density is improved, but over-burden occurs in the top device region
Solution Approach 1:
The top device region is segmented into multiple silicon sheets separated by separation layers. This segmentation distributes the mechanical and electrical burden across multiple discrete components rather than concentrating stress in a single continuous structure, reducing over-burden effects.
3Ease of manufacture
If conventional stacked FET fabrication is used, then manufacturing process is simplified, but self-aligned integration is difficult to achieve
Solution Approach 1:
The inner spacer epitaxy is formed preliminarily before the top source-drain epitaxy. This preliminary formation establishes a predefined reference structure that guides subsequent alignment steps, enabling self-aligned integration where the top device automatically aligns with the bottom device through the spacer's geometric constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances integration density, prevents direct shorts, and simplifies fabrication by eliminating the need for a third dielectric layer, while allowing for vertical confinement and self-aligned integration of dual epitaxy, improving the reliability and efficiency of stacked FET devices.
Implementation Method 1
a first source-drain epitaxy in direct contact with the first set of silicon sheets
Data Source
AI summary
A semiconductor device includes a bottom device, a top device, and a spacer. The bottom device includes a first set of silicon sheets and a first source-drain epitaxy in direct contact with the first set of silicon sheets. The top device includes a second set of silicon sheets, a set of separation layers, and a second source-drain epitaxy. Each silicon sheet of the second set of silicon sheets is separated by a separation layer of the set of separation layers. The second source-drain epitaxy is arranged in direct contact with the second set of silicon sheets. The spacer is arranged between the first source-drain epitaxy and the second source-drain epitaxy and is arranged between each silicon sheet of the second set of silicon sheets.