Stacked Nanosheet FET Staircase Structure for Short-Free Contacts
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Solution Overview
Problem
The fabrication of stacked nanosheet FET devices presents challenges, particularly in forming staircase structures where the top active area is smaller than the bottom, due to issues during gate, spacer, and source/drain epitaxy formation, which can lead to electrical shorts and manufacturing complexities.
Innovation Solution
The method involves defining the size of the top and bottom active regions using hardmasks, patterning the nanosheet stack to ensure equal sizes, forming dummy gates and spacers, partially recessing the dummy gate, and selectively removing hardmasks to achieve a staircase structure without electrical shorts, allowing for proper contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked nanosheet FET devices are fabricated with staircase structures, then device density and performance are improved, but manufacturing complexity increases due to challenges in gate, spacer, and source/drain epitaxy formation
Solution Approach 1:
The patent divides the fabrication process into distinct stages: first forming the nanosheet stack with equal-sized top and bottom regions, then selectively removing material from the bottom region to create the staircase structure. This segmentation allows each stage to be optimized independently, reducing overall manufacturing complexity while achieving the desired high-density stacked configuration
Solution Approach 2:
The patent performs preliminary patterning of the nanosheet stack to establish equal-sized regions before forming the gate and spacers. This preliminary action simplifies subsequent processing by providing a symmetric starting structure, avoiding the complexity of forming asymmetric staircase structures during gate formation
2Area of stationary object
If stacked nanosheet FETs are fabricated, then device footprint is reduced, but manufacturing precision requirements increase due to alignment challenges
Solution Approach 1:
The patent creates an asymmetric staircase structure from an initially symmetric nanosheet stack by selectively removing material from the bottom region. This approach allows the top and bottom regions to be formed with equal precision during the symmetric phase, then introduces the asymmetric staircase geometry afterward when alignment challenges are no longer an issue
Solution Approach 2:
The patent segments the structure formation into two phases: first forming the symmetric nanosheet stack with precise alignment, then separately creating the asymmetric staircase structure. This segmentation allows each phase to be optimized for its specific requirements, maintaining high alignment precision while achieving the desired compact footprint
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a bottom field effect transistor (FET); a top FET stacked over the bottom FET, where the top FET has a smaller active area than the bottom FET; a bottom gate formed in contact with the bottom FET; a top gate formed in contact with the top FET; and a bottom contact formed adjacent to the top gate, wherein an inner spacer is formed between the bottom contact and the top gate.